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AX88780
29
ASIX ELECTRONICS CORPORATION
4.31 GPIO_CTRL--GPIO Control Register
Offset Address = 0xFC8C Default = 0x0000_0003
Field
Name
Type
Default
31:10
-
R
All 0’s
9
GPIO1S
R/W
0
Description
Reserved
GPIO1 Status
This bit stands for the pin status of GPIO1 when it is set to input mode.
1 = high state
0 = low state
GPIO0 Status
This bit stands for the pin status of GPIO0 when it is set to input mode.
1 = high state
0 = low state
Reserved
GPIO1 Mode Direction
This field defines the direction of GPIO1 pin.
1 = input mode
0 = output mode
GPIO0 Mode Direction
This field defines the direction of GPIO pin.
1 = input mode
0 = output mode
8
GPIO0S
R/W
0
7:2
1
-
R
All 0’s
1
GPIO1DIR R/W
0
GPIO0DIR R/W
1
Note: For output mode, software must firstly set the bit0 or bit1 to output mode then set bit8 or bit9.
4.32 RXINDICATOR--Receive Indicator Register
Offset Address= 0xFC90 Default = 0x0000_0000
Field
Name
Type
Default
31:1
-
R
All 0’s
0
RXSTART R/W
0
Description
Reserved
Receive Start
Driver set this bit to start or end receive operation from RX buffer of MAC.
1= Start read RX buffer
0= End read RX buffer
4.33 TXST--TX Status Register
Offset Address = 0xFC94 Default = 0x0000_0000
Field
Name
Type
Default
31:4
-
R
All 0’s
3
TXD3FAIL R
0
Description
Reserved
TX Descriptor3 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 3.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor2 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 2.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor1 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 1.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor0 Transmit Fail
When this bit is set 1, it means MAC fails in transmission of descriptor 0.
This bit will be self-cleared when driver reads TXST register.
2
TXD2FAIL R
0
1
TXD1FAIL R
0
0
TXD0FAIL R
0