參數(shù)資料
型號(hào)： AT90S8515-8JC
廠商： Atmel
文件頁數(shù)： 59/112頁
文件大?。?/td> 0K
描述： IC MCU 8K FLSH 8MHZ 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（4K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
50
AT90S8515
0841G–09/01
Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI Mode when set (one), and Slave SPI Mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master Mode.
Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 36 and Figure 37 for additional information.
Bit 2 – CPHA: Clock Phase
Refer to Figure 36 or Figure 37 for the functionality of this bit.
Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the oscillator
clock frequency fcl is shown in Table 16.
SPI Status Register – SPSR
Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master Mode, this will also set the SPIF flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register when SPIF is set
(one), then by accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister when WCOL is set (one), and then by accessing the SPI Data Register.
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8515 and will always read as zero.
The SPI interface on the AT90S8515 is also used for program memory and EEPROM
downloading or uploading. See page 86 for serial programming and verification.
Table 16. Relationship between SCK and the Oscillator Frequency
SPR1
SPR0
SCK Frequency
00
f
cl/4
01
f
cl/16
10
fcl/64
11
f
cl/128
Bit
765
432
10
$0E ($2E)
SPIF
WCOL
–
SPSR
Read/Write
RR
RRR
Initial Value
0
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