參數(shù)資料
型號(hào)： AT90S8515-8JC
廠商： Atmel
文件頁(yè)數(shù)： 33/112頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8K FLSH 8MHZ 44PLCC
標(biāo)準(zhǔn)包裝： 27
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（4K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
27
AT90S8515
0841G–09/01
Bit 6 – INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0, becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT0 in GIMSK are set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by
writing a logical “1” to it. This flag is always cleared when INT0 is configured as level
interrupt.
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8515 and always read as zero.
Timer/Counter Interrupt Mask
Register – TIMSK
Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at
vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the
OCF1A bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at
vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the
OCF1B bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 4 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and always reads zero.
Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt
(at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e.,
when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and always reads zero.
Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register (TIFR).
Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8515 and always reads zero.
Bit
7
6
5
4
3
2
1
0
$39 ($59)
TOIE1
OCIE1A
OCIE1B
–
TICIE1
–
TOIE0
–
TIMSK
Read/Write
R/W
R
R/W
R
R/W
R
Initial Value
0
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