參數(shù)資料
型號： AT90S8515-8JC
廠商： Atmel
文件頁數(shù)： 53/112頁
文件大?。?/td> 0K
描述： IC MCU 8K FLSH 8MHZ 44PLCC
標準包裝： 27
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 8KB（4K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
45
AT90S8515
0841G–09/01
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the
selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE
has been set (one) by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for a EEPROM write procedure.
Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, oth-
erwise no EEPROM write takes place. The following procedure should be followed
when writing the EEPROM (the order of steps 2 and 3 is unessential):
1.
Wait until EEWE becomes zero.
2.
Write new EEPROM address to EEARL and EEARH (optional).
3.
Write new EEPROM data to EEDR (optional).
4.
Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to
the EEMWE bit, the EEWE bit must be written to zero in the same cycle).
5.
Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.
When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has
elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEWE has been set, the CPU is
halted for two cycles before the next instruction is executed.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR registers will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the global interrupt flag cleared during the four last steps to avoid these problems.
Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.
The EEPROM read access takes one instruction and there is no need to poll the EERE
bit. When EERE has been set, the CPU is halted for four cycles before the next instruc-
tion is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress when new data or address is written to the EEPROM I/O registers, the
write operation will be interrupted and the result is undefined.
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