參數資料
型號: AT90S2313-10PC
廠商: Atmel
文件頁數: 60/92頁
文件大小: 0K
描述: IC MCU 2K FLSH 10MHZ UART 20DIP
標準包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 15
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
1997 Microchip Technology Inc.
DS30234D-page 63
PIC16C6X
6.0
OVERVIEW OF TIMER
MODULES
All PIC16C6X devices have three timer modules except
for the PIC16C61, which has one timer module. Each
module can generate an interrupt to indicate that an
event has occurred (i.e., timer overow). Each of these
modules are detailed in the following sections. The
timer modules are:
Timer0 module (Section 7.0)
Timer1 module (Section 8.0)
Timer2 module (Section 9.0)
6.1
Timer0 Overview
The Timer0 module is a simple 8-bit overow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock. When the clock
source is an external clock, the Timer0 module can be
selected to increment on either the rising or falling
edge.
The Timer0 module also has a programmable pres-
caler option. This prescaler can be assigned to either
the Timer0 module or the Watchdog Timer. Bit PSA
(OPTION<3>) assigns the prescaler, and bits PS2:PS0
(OPTION<2:0>) determine the prescaler value. TMR0
can increment at the following rates: 1:1 when the pres-
caler is assigned to Watchdog Timer, 1:2, 1:4, 1:8,
1:16, 1:32, 1:64, 1:128, and 1:256.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre-
quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
6.2
Timer1 Overview
Timer1 is a 16-bit timer/counter. The clock source can
be either the internal system clock (Fosc/4), an external
clock, or an external crystal. Timer1 can operate as
either a timer or a counter. When operating as a
counter (external clock source), the counter can either
operate synchronized to the device or asynchronously
to the device. Asynchronous operation allows Timer1 to
operate during sleep, which is useful for applications
that require a real-time clock as well as the power sav-
ings of SLEEP mode.
TImer1 also has a prescaler option which allows TMR1
to increment at the following rates: 1:1, 1:2, 1:4, and
1:8. TMR1 can be used in conjunction with the Capture/
Compare/PWM module. When used with a CCP mod-
ule, Timer1 is the time-base for 16-bit capture or 16-bit
compare and must be synchronized to the device.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
6.3
Timer2 Overview
Timer2 is an 8-bit timer with a programmable prescaler
and a programmable postscaler, as well as an 8-bit
Period Register (PR2). Timer2 can be used with the
CCP module (in PWM mode) as well as the Baud Rate
Generator for the Synchronous Serial Port (SSP). The
prescaler option allows Timer2 to increment at the fol-
lowing rates: 1:1, 1:4, and 1:16.
The postscaler allows TMR2 register to match the
period register (PR2) a programmable number of times
before generating an interrupt. The postscaler can be
programmed from 1:1 to 1:16 (inclusive).
6.4
CCP Overview
The CCP module(s) can operate in one of three modes:
16-bit capture, 16-bit compare, or up to 10-bit Pulse
Width Modulation (PWM).
Capture mode captures the 16-bit value of TMR1 into
the CCPRxH:CCPRxL register pair. The capture event
can be programmed for either the falling edge, rising
edge, fourth rising edge, or sixteenth rising edge of the
CCPx pin.
Compare mode compares the TMR1H:TMR1L register
pair to the CCPRxH:CCPRxL register pair. When a
match occurs, an interrupt can be generated and the
output pin CCPx can be forced to a given state (High or
Low) and Timer1 can be reset. This depends on control
bits CCPxM3:CCPxM0.
PWM mode compares the TMR2 register to a 10-bit
duty cycle register (CCPRxH:CCPRxL<5:4>) as well as
to an 8-bit period register (PR2). When the TMR2 reg-
ister = Duty Cycle register, the CCPx pin will be forced
low. When TMR2 = PR2, TMR2 is cleared to 00h, an
interrupt can be generated, and the CCPx pin (if an out-
put) will be forced high.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
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