參數(shù)資料
型號(hào): AT90S2313-10PC
廠商: Atmel
文件頁(yè)數(shù): 26/92頁(yè)
文件大小: 0K
描述: IC MCU 2K FLSH 10MHZ UART 20DIP
標(biāo)準(zhǔn)包裝: 18
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 10MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 2KB(1K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
32
AT90S2313
0839I–AVR–06/02
Bits 1, 0 – PWM11, PWM10: Pulse Width Modulator Select Bits
These bits select PWM operation of Timer/Counter1 as specified in Table 9. This mode
is described on page 35.
Timer/Counter1 Control
Register B – TCCR1B
Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is
disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP
(input capture pin) as specified. When the ICNC1 bit is set (one), four successive sam-
ples are measured on the ICP (input capture pin), and all samples must be high/low
according to the input capture trigger specification in the ICES1 bit. The actual sampling
frequency is the XTAL clock frequency.
Bit 6 – ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While
the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Cap-
ture Register (ICR1) on the rising edge of the input capture pin (ICP).
Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read zero.
Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 contin-
ues counting and is unaffected by a compare match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used,
and the Compare A Register is set to C, the timer will count as follows if CTC1 is set:
... | C-2| C-1| C| 0| 1|...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 |...
In PWM mode, this bit has no effect.
Table 9. PWM Mode Select
PWM11
PWM10
Description
0
PWM operation of Timer/Counter1 is disabled
0
1
Timer/Counter1 is an 8-bit PWM
1
0
Timer/Counter1 is a 9-bit PWM
1
Timer/Counter1 is a 10-bit PWM
Bit
7
6
5
4
3210
$2E ($4E)
ICNC1
ICES1
––
CTC1
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial value
0
00
0000
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