參數(shù)資料
型號(hào): AT32AP7002-CTUR
廠商: Atmel
文件頁(yè)數(shù): 9/83頁(yè)
文件大?。?/td> 0K
描述: IC MCU AVR32 196-CBGA
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR®32 AP7
核心處理器: AVR
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC,PS2,SPI,SSC,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: D/A 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 196-TFBGA,CSBGA
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT32AP7002-CTURDKR
17
32054F–AVR32–09/09
AT32AP7002
6.
AVR32 AP CPU
Rev.: 1.0.0.0
This chapter gives an overview of the AVR32 AP CPU. AVR32 AP is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, caches and MMU is
presented. For further details, see the AVR32 Architecture Manual and the AVR32 AP Technical
Reference Manual.
6.1
AVR32 Architecture
AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost-
sensitive embedded applications, with particular emphasis on low power consumption and high
code density. In addition, the instruction set architecture has been tuned to allow a variety of
microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirements, a compact code size also contributes to the core’s low power characteris-
tics. The processor supports byte and half-word data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, half-word, word and double word data
with automatic sign- or zero extension of half-word and byte data.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an extended format with a larger immediate. In this way, the compiler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases performance, allowing an addition and a data move in the same instruction in a
single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
The register file is organized as sixteen 32-bit registers and includes the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.
6.2
The AVR32 AP CPU
AVR32 AP targets high-performance applications, and provides an advanced OCD system, effi-
cient data and instruction caches, and a full MMU. Figure 6-1 on page 18 displays the contents
of AVR32 AP.
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