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參數(shù)資料
| 型號(hào)： | AT32AP7002-CTUR |
| 廠商： | Atmel |
| 文件頁數(shù)： | 62/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU AVR32 196-CBGA |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AVR®32 AP7 |
| 核心處理器： | AVR |
| 芯體尺寸： | 32-位 |
| 速度： | 150MHz |
| 連通性： | EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 85 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | D/A 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 196-TFBGA，CSBGA |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AT32AP7002-CTURDKR |
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2011 Microchip Technology Inc.
DS70118J-page 57
dsPIC30F2010
9.0
TIMER1 MODULE
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1 depicts the simplified block diagram of the
16-bit Timer1 Module.
The following sections provide a detailed description of
the operational modes of the timers, including setup
and control registers along with associated block
diagrams.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the real-time clock, or operate as a
free running interval timer/counter. The 16-bit timer has
the following modes:
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
Timer gate operation
Selectable prescaler settings
Timer operation during CPU Idle and Sleep
modes
Interrupt on 16-bit period register match or falling
edge of external gate signal
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the period register PR1, then
resets to ‘0’ and continues to count.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to ‘0’ and continues.
When the timer is configured for the Asynchronous
mode of operation and the CPU goes into the Idle
mode, the timer will stop incrementing if TSIDL = 1.
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
Note:
Timer1 is a ‘Type A’ timer. Refer to the
specifications for the Type A timer in
for details.
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