參數資料
| 型號： | AT32AP7002-CTUR |
| 廠商： | Atmel |
| 文件頁數： | 79/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU AVR32 196-CBGA |
| 產品培訓模塊： | MCU Product Line Introduction |
| 標準包裝： | 1 |
| 系列： | AVR®32 AP7 |
| 核心處理器： | AVR |
| 芯體尺寸： | 32-位 |
| 速度： | 150MHz |
| 連通性： | EBI/EMI，I²C，MMC，PS2，SPI，SSC，UART/USART，USB |
| 外圍設備： | AC'97，DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數： | 85 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 1.95 V |
| 數據轉換器： | D/A 2x16b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 196-TFBGA，CSBGA |
| 包裝： | 標準包裝 |
| 其它名稱： | AT32AP7002-CTURDKR |
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dsPIC30F2010
DS70118J-page 72
2011 Microchip Technology Inc.
12.1
Timer2 and Timer3 Selection Mode
Each output compare channel can select between one
of two 16-bit timers: Timer2 or Timer3.
The selection of the timers is controlled by the OCTSEL
bit (OCxCON<3>). Timer2 is the default timer resource
for the Output Compare module.
12.2
Simple Output Compare Match
Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 001,
010
or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
Compare forces I/O pin low
Compare forces I/O pin high
Compare toggles I/O pin
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
12.3
Dual Output Compare Match Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is config-
ured for one of two Dual Output Compare modes,
which are:
Single Output Pulse mode
Continuous Output Pulse mode
12.3.1
SINGLE PULSE MODE
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):
Determine instruction cycle time TCY.
Calculate desired pulse width value based on TCY.
Calculate time to start pulse from timer start value
of 0x0000.
Write pulse width start and stop times into OCxR
and OCxRS compare registers (x denotes
channel 1, 2).
Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
Set OCM<2:0> = 100.
Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
12.3.2
CONTINUOUS PULSE MODE
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
Determine instruction cycle time TCY.
Calculate desired pulse value based on TCY.
Calculate timer to start pulse width from timer start
value of 0x0000.
Write pulse width start and stop times into OCxR
and OCxRS (x denotes channel 1, 2) compare
registers, respectively.
Set timer period register to value equal to, or
greater than, value in OCxRS compare register.
Set OCM<2:0> = 101.
Enable timer, TON (TxCON<15>) = 1.
12.4
Simple PWM Mode
When control bits OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is config-
ured for the PWM mode of operation. When configured
for the PWM mode of operation, OCxR is the main latch
(read-only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1.
Set the PWM period by writing to the appropriate
period register.
2.
Set the PWM duty cycle by writing to the OCxRS
register.
3.
Configure the output compare module for PWM
operation.
4.
Set the TMRx prescale value and enable the
Timer, TON (TxCON<15>) = 1.
12.4.1
INPUT PIN FAULT PROTECTION
FOR PWM
When control bits OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again config-
ured for the PWM mode of operation, with the
additional feature of input fault protection. While in this
mode, if a logic ‘0’ is detected on the OCFA/B pin, the
respective PWM output pin is placed in the high-imped-
ance input state. The OCFLT bit (OCxCON<4>)
indicates whether a Fault condition has occurred. This
state will be maintained until both of the following
events have occurred:
The external Fault condition has been removed.
The PWM mode has been re-enabled by writing
to the appropriate control bits.
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