參數(shù)資料
型號: AS3517
廠商: ams
文件頁數(shù): 72/94頁
文件大?。?/td> 0K
描述: IC CODEC AFE AUDIO STER 81-CTBGA
標(biāo)準包裝: 250
類型: 音頻編解碼器
應(yīng)用: 便攜式音頻,電話
安裝類型: 表面貼裝
封裝/外殼: 81-TFBGA
供應(yīng)商設(shè)備封裝: 81-CTBGA(9x9)
包裝: 托盤
AS3517 V17
Data Sheet, Confidential
2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Table 73 PMU CVDD1 Register
Name
Base
Default
PMU CVDD1
2-wire serial
00h
CVDD1 DC/DC Buck Regulator Control Register
Offset: 17h-3
This is an extended register and needs to be enabled by writing 011b to Reg. 18h first.
This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
7
SKIP_OFF_CVDD1
0
R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without
load)
6
PROG_CVDD1
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-3 register
0: VPRGx pins controlled
1: Register controlled
5:0
VSEL_CVDD1
00000
R/W
The voltage select bits set the DC/DC output voltage level and
power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD1=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
Table 74 PMU CVDD2 Register
Name
Base
Default
PMU CVDD2
2-wire serial
0x00
CVDD2 DC/DC Buck Regulator Control Register
Offset: 17h-4
This is an extended register and needs to be enabled by writing 100bto Reg. 18h first.
This register is reset at a DVDD-POR.
Bit
Bit Name
Default
Access
Bit Description
7
SKIP_OFF_CVDD2
0
R/W
Disables pulse skip mode
0: 170mA current force / pulse skip mode enabled
1: current force / pulse skip mode disabled (only ON without
load)
6
PROG_CVDD2
0
R/W
Enables settings either selected by external pin (VPRGx) or
settings stored in the 17h-4 register
0: VPRGx pins controlled
1: Register controlled
5:0
VSEL_CVDD2
00000
R/W
The voltage select bits set the DC/DC output voltage level and
power the DC/DC converter down.
00000: DC/DC powered down
01h until 38h in 50mV steps
CVDD2=0.6V+VSEL_CVDD1*50mV
(0.65V until 3.4V)
38h until 3Fh = 3.4V (no change)
Revision 1v3
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- 93
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AG
Technical
content
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