參數(shù)資料
型號(hào)： AS3517
廠商： ams
文件頁數(shù)： 17/94頁
文件大?。?/td> 0K
描述： IC CODEC AFE AUDIO STER 81-CTBGA
標(biāo)準(zhǔn)包裝： 250
類型： 音頻編解碼器
應(yīng)用： 便攜式音頻，電話
安裝類型： 表面貼裝
封裝/外殼： 81-TFBGA
供應(yīng)商設(shè)備封裝： 81-CTBGA（9x9）
包裝： 托盤
AS3517 V17
Data Sheet, Confidential
2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
9.1.5
DAC, ADC and I2S Digital Audio Interface
Input
The AFE receives serialized audio data for the DAC via pin SDI. The output of the DAC is fed through a volume control to the mixer stage
and to the multiplexers of line output and headphone amplifiers.
This serialized audio data is a digital audio data stream with the left and the right audio channels multiplexed into one bit-stream. Via pin
LRCLK the alignment clock is input to the DAC digital filters. LRCLK (Left Right Clock) indicates whether the serial bit-stream received via
pin SDI, represents right channel or left channel audio data. Via pin SCLK the bit clock for the serial bit-stream is signalled. SDI and
LRCLK are synchronous with SCLK. SDI is an inputs; LRCLK and SCLK are either inputs or outputs depending on the master/slave
operation mode. SDO is not used.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
Output
This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a
volume control to the 20 bit ADC. The digital output is done via an I2S interface.
The AFE sends serialized audio data from the ADC via pin SDO. This serialized audio data is a digital audio data stream with the left and
the right audio channels multiplexed into one bit-stream. Via pin LRCLK the alignment clock is signalled to the connected devices (e.g.
CPU). LRCLK (Left Right Clock) indicates whether the serial bit-stream sent via pin SDI, presents right channel or left channel audio data.
Via pin SCLK the bit clock for the serial bit-stream is signalled. SDO and LRCLK are synchronous with SCLK. SDO is an output; LRCLK
and SCLK are either inputs or outputs depending on the master/slave operation mode. SDI is not used.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.
I2S Modes
The AFE can be operated either in Master Mode, Slave Mode or additionally in Slave Mode with the master clock directly signalled via pin
PWGD (pin PWGD is multiplexed for I2S Direct Mode). The difference between Master and Slave Mode is whether the AFE or the
externally attached decoder/encoder device is generating the interface clocks. The master clock (MCLK) is the necessary internal over-
sampling clock for the DAC and ADC (e.g. 256*fs, fs=audio sampling frequency).
Due to the internal structure left and right audio samples are exchanged in I2S Direct Mode.
In Slave Mode the PLL generates the master clock based on LRCLK. Thus the PLL needs to be preset to the expected sampling
frequency. The ranges are 8kS-12kS (8kHz-12kHz) and 16kS-48kS (16kHz-48kHz). Please refer to register 0x1Dh.
Table 19 I2S Modes
Master Mode
Slave Mode, internal PLL of the AFE generates MCLK
Slave Mode with I2S direct, the master clock is signalled
Revision 1v3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS3517-T 功能描述:IC CODEC AFE AUDIO STER 81-CTBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AS3518 功能描述:IC CODEC AFE AUDIO STER 64-CABGA RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AS3518-ECTP 功能描述:IC CODEC AFE AUDIO STER 64-CABGA RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AS3518-ECTS 功能描述:IC AUDIO FRONT END STER 64CTBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
AS3518-T 功能描述:IC CODEC AFE AUDIO STER 64-CABGA RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
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