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鍨嬭櫉锛� APA750-FGG896
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 108/178闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA PROASIC+ 750K 896-FBGA
妯欐簴鍖呰锛� 27
绯诲垪锛� ProASICPLUS
RAM 浣嶇附瑷堬細 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 562
闁€鏁�(sh霉)锛� 750000
闆绘簮闆诲锛� 2.3 V ~ 2.7 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 896-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 896-FBGA锛�31x31锛�
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ProASICPLUS Flash Family FPGAs
v5.9
2-25
Design Environment
The ProASICPLUS family of FPGAs is fully supported by
both Actel's Libero Integrated Design Environment
(IDE) and Designer FPGA Development software. Actel
Libero IDE is an integrated design manager that
seamlessly integrates design tools while guiding the user
through the design flow, managing all design and log
files, and passing necessary design data among tools.
Additionally, Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment (see Actel鈥檚
website for more information about Libero IDE). Libero
IDE includes Synplify AE from Synplicity, ViewDraw
AE from Mentor Graphics, ModelSim HDL Simulator
from Mentor Graphics, WaveFormer Lite AE from
SynaptiCAD, PALACE AE Physical Synthesis from
Magma, and Designer software from Actel.
PALACE is an effective tool when designing with
ProASICPLUS. PALACE AE Physical Synthesis from Magma
takes an EDIF netlist and optimizes the performance of
ProASICPLUS devices through a physical placement-driven
process, ensuring that timing closure is easily achieved.
Actel's Designer software is a place-and-route tool that
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
Timer 鈥� A world-class integrated static timing
analyzer and constraints editor that supports
timing-driven place-and-route
NetlistViewer 鈥� A design netlist schematic viewer
ChipPlanner 鈥� A graphical floorplanner viewer and
editor
SmartPower 鈥� Allows the designer to quickly
estimate the power consumption of a design
PinEditor 鈥� A graphical application for editing pin
assignments and I/O attributes
I/O Attribute Editor 鈥� Displays all assigned and
unassigned I/O macros and their attributes in a
spreadsheet format
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of place-and-route. Additionally, Actel鈥檚 back-annotation
flow is compatible with all the major simulators. Another
tool included in the Designer software is the SmartGen
macro
builder,
which
easily
creates
popular
and
commonly used logic functions for implementation into
your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
ISP
The user can generate *.bit or *.stp programming files
from the Designer software and can use these files to
program a device.
ProASICPLUS devices can be programmed in-system. For
more information on ISP of ProASICPLUS devices, refer to
ProASICPLUS Devices application notes. Prior to being
programmed for the first time, the ProASICPLUS device I/Os
are in a tristate condition with the pull-up resistor option
enabled.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
HSC49DRYN-S93 CONN EDGECARD 98POS DIP .100 SLD
A3PE3000L-FGG484I IC FPGA 1KB FLASH 3M 484-FBGA
170-015-172L000 CONN DB15 CRIMP MALE TIN
HSC49DRYH-S93 CONN EDGECARD 98POS DIP .100 SLD
170-037-172L030 CONN DB37 CRIMP MALE TIN
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鍙冩暩(sh霉)鎻忚堪
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