
8
Biasing and Operation
AMMP-5024 is biased with a single positive drain supply
(Vdd) a negative gate supply (Vg1) and has a positive
control gate supply (Vg2). For best overall performance
the recommended bias condition for the AMMP-5024 is
Vdd =7V and Idd = 200 mA. To achieve this drain current
level, Vg1 is typically between –2.5 to –3.5V. Typically, DC
current flow for Vg1 is –10 mA. Open circuit is the default
setting for Vg2 when not utilizing gain control.
Using the simplest form of assembly, the device is capable
of delivering flat gain over a 2–40 GHz range. However,
this device is designed with DC coupled RF I/O ports, and
operation may be extended to lower frequencies (<2
GHz) through the use of off-chip low-frequency extension
circuitry and proper external biasing components. With
low frequency bias extension it may be used in a variety
of time domain applications (through 40 Gb/s).
When bypass capacitors are connected to the AUX pads,
the low frequency limit is extended down to the corner
frequency determined by the bypass capacitor and the
combination of the on-chip 50 ohm load and small de-
queing resistor. At this frequency the small signal gain
will increase in magnitude and stay at this elevated level
down to the point where the Caux bypass capacitor
acts as an open circuit, effectively rolling off the gain
completely.The low frequency limit can be approximated
from the following equation:
1
fCaux =
2pCaux (Ro + RDEQ)
where:
Ro is the 50Ω gate or drain line termination resistor.
RDEQ is the small series dequeing resistor and 10Ω.
Cauxisthecapacitanceofthebypasscapacitorconnected
to the AUX Drain and AUX Gate pad in farads.
With the external bypass capacitors connected to the
AUX gate and AUX drain pads, gain will show a slight
increase between 1.0 and 1.5 GHz. This is due to a series
combination of Caux and the on-chip resistance but
is exaggerated by the parasitic inductance (Lc) of the
bypass capacitor and the inductance of the bond wire
(Ld).
Input and output RF ports are DC coupled; therefore, DC
decoupling capacitors are required if there are DC paths.
(Do not attempt to apply bias to these pads.)
Recommended SMT Attachment
The AMMP Packaged Devices are compatible with high
volume surface mount PCB assembly processes. The
PCB material and mounting pattern, as defined in the
data sheet, optimizes RF performance and is strongly
recommended. An electronic drawing of the land pattern
is available upon request from Avago Sales & Application
Engineering.
Manual Assembly
1. Follow ESD precautions while handling packages.
2. Handling should be along the edges with tweezers.
3. Recommended attachment is conductive solder
paste. Please see recommended solder reflow profile.
Conductive epoxy is not recommended. Hand
soldering is not recommended.
4. Apply solder paste using a stencil printer or dot
placement. The volume of solder paste will be
dependent on PCB and component layout and should
be controlled to ensure consistent mechanical and
electrical performance.
5. Follow solder paste and vendor’s recommendations
when developing a solder reflow profile. A standard
profile will have a steady ramp up from room
temperature to the pre-heat temperature to avoid
damage due to thermal shock.
6. Packages have been qualified to withstand a peak
temperature of 260°C for 20 seconds. Verify that the
profile will not expose device beyond these limits.
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads. The recommended stencil layout
is shown in Figure 19. The stencil has a solder paste
deposition opening approximately 70% to 90% of the PCB
pad. Reducing stencil opening can potentially generate
more voids underneath. On the other hand, stencil
openings larger than 100% will lead to excessive solder
paste smear or bridging across the I/O pads. Considering
the fact that solder paste thickness will directly affect the
quality of the solder joint, a good choice is to use a laser
cut stencil composed of 0.127 mm (5 mils) thick stainless
steel which is capable of producing the required fine
stencil outline.
The combined PCB and stencil layout is shown in Figure 20.