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參數(shù)資料
| 型號： | AM49LV6408MT10IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA69 |
| 封裝： | 10 X 8 MM, 1.20 MM HEIGHT, FBGA-69 |
| 文件頁數(shù)： | 58/63頁 |
| 文件大小： | 540K |
| 代理商： | AM49LV6408MT10IT |
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56
Am49LV6408M
November 5, 2003
A D V A N C E I N F O R M A T I O N
PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 28.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
55
70
t
WC
Write Cycle Time
Min
55
70
ns
t
Cw
Chip Enable to End of Write
Min
45
55
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
45
55
ns
t
BW
UB#s, LB#s to End of Write
Min
45
55
ns
t
WP
Write Pulse Time
Min
45
55
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
25
t
DW
Data to Write Time Overlap
Min
40
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
Min
5
ns
Address
CE1#s
Data Undefined
WE#
Data In
Data Out
t
WC
t
CW
(See Note 1)
t
AW
High-Z
High-Z
Data Valid
CE2s
t
(See Note 1)
t
(See Note 4)
t
AS
(See Note 3)
t
WR
t
DW
t
DH
t
OW
t
WHZ
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| AM49LV6408MT11IT | Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) |
| AM49LV6408MT15IT | Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM49LV6408MT11I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM |
| AM49LV6408MT11IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) |
| AM49LV6408MT15I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM |
| AM49LV6408MT15IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) |
| AM49PDL127AH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM |
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