參數(shù)資料
型號(hào)： AM49LV6408MT10IT
廠(chǎng)商： SPANSION LLC
元件分類(lèi)： 存儲(chǔ)器
英文描述： Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA69
封裝： 10 X 8 MM, 1.20 MM HEIGHT, FBGA-69
文件頁(yè)數(shù)： 56/63頁(yè)
文件大?。?/td> 540K
代理商： AM49LV6408MT10IT
54
Am49LV6408M
November 5, 2003
A D V A N C E I N F O R M A T I O N
PSEUDO SRAM AC CHARACTERISTICS
Power Up Time
When powering up the pSRAM, maintain V
CC
s for 100 μs minimum with CE#1ps at V
IH
.
Read Cycle
Notes:
1. CE1#ps = OE# = V
IL
, CE2ps = WE# = V
IH
, UB#ps and/or LB#ps = V
IL
2. Do not access device with cycle timing shorter than t
RC
for continuous periods < 10 μs.
Figure 26.
Pseudo SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
Speed
Unit
15
10, 11
t
RC
Read Cycle Time
Min
55
70
ns
t
AA
Address Access Time
Max
55
70
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
55
70
ns
t
OE
Output Enable Access Time
Max
30
35
ns
t
BA
LB#ps, UB#ps to Access Time
Max
55
70
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#ps Low and CE2ps High) to Low-Z
Output
Min
5
ns
t
BLZ
UB#ps, LB#ps Enable to Low-Z Output
Min
5
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
20
25
ns
t
BHZ
UB#ps, LB#ps Disable to High-Z Output
Max
20
25
ns
t
OHZ
Output Disable to High-Z Output
Max
20
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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AM49LV6408MT15I 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit) pseudo Static RAM
AM49LV6408MT15IT 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8 Mbit (512K x 16-Bit)
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