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| 型號： | AM49BDS640AHD9I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 44/84頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AM49BDS640AHD9I |
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42
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
Table 16.
DQ6 and DQ2 Indications
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 7, “Toggle Bit Algorithm,” on page 41
for
the following discussion. Whenever the system initially
begins reading toggle bit status, it must read DQ7–DQ0
at least twice in a row to determine whether a toggle bit
is toggling. Typically, the system would note and store
the value of the toggle bit after the first read. After the
second read, the system would compare the new value
of the toggle bit with the first. If the toggle bit is not tog-
gling, the device has completed the program or erase
operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (
Figure 7, “Toggle
Bit Algorithm,” on page 41
).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully com-
pleted.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can change a
“0” back to a “1.” Under this condition, the device halts
the operation, and when the timing limit has been
exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the
reset command to return to the read mode (or to the
erase-suspend-read mode if a bank was previously in
the erase-suspend-program mode).
If device is
and the system reads
then DQ6
and DQ2
programming,
at any address,
toggles,
does not toggle.
actively erasing,
at an address within a sector
selected for erasure,
toggles,
also toggles.
at an address within sectors not
selected for erasure,
toggles,
does not toggle.
erase suspended,
at an address within a sector
selected for erasure,
does not toggle,
toggles.
at an address within sectors not
selected for erasure,
returns array data,
returns array data. The system can read
from any sector not selected for erasure.
programming in
erase suspend
at any address,
toggles,
is not applicable.
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