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參數(shù)資料
| 型號(hào)： | AM49BDS640AHD9I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 43/84頁 |
| 文件大小： | 763K |
| 代理商： | AM49BDS640AHD9I |
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December 5, 2003
Am49BDS640AH
41
A D V A N C E I N F O R M A T I O N
Figure 7.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode informa-
tion. Refer to
Table 16, “DQ6 and DQ2 Indications,” on
page 42
to compare outputs for DQ2 and DQ6.
See the following for additional information:
Figure 7,
“Toggle Bit Algorithm,” on page 41, “DQ6: Toggle Bit I”
on page 40, Figure 38, “Toggle Bit Timings
(During Embedded Algorithm),” on page 67
, and
Table 16, “DQ6 and DQ2 Indications,” on page 42
.
START
No
Yes
Yes
DQ5 = 1
No
Yes
DQ6 = Toggle
No
Read Byte
(DQ7-DQ0)
Address = VA
DQ6 = Toggle
Read Byte Twice
(DQ7-DQ0)
Adrdess = VA
Read Byte
(DQ7-DQ0)
Address = VA
FAIL
PASS
Note:
The system should recheck the toggle bit even if DQ5 =
“1” because the toggle bit may stop toggling as DQ5 changes
to “1.” See the subsections on DQ6 and DQ2 for more
information.
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