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參數(shù)資料
| 型號： | AM49BDS640AHD8I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 74/84頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AM49BDS640AHD8I |
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72
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a
bank in the process of performing an erase or program.
Figure 44.
Latency with Boundary Crossing
into Program/Erase Bank
CLK
Address (hex)
C60
C61
C62
C63
C63
C63
C64
D60
D61
D62
D63
Read Status
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 64 words, beginning at address
00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
3C
3D
3E
3F
3F
3F
40
latency
RDY(2)
latency
t
RACC
t
RACC
t
RACC
t
RACC
Invalid
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