參數(shù)資料
型號(hào)： AM49BDS640AHD8I
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA89
封裝： 10 X 8 MM, FBGA-89
文件頁數(shù)： 62/84頁
文件大?。?/td> 763K
代理商： AM49BDS640AHD8I
60
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. Asynchronous mode allows both Asynchronous and Synchronous program operation. Synchronous mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In
synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of
CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
Parameter
Description
66 MHz
54 MHz
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
50
55
ns
t
AVWL
t
AS
Address Setup
Time (Notes 2, 3)
Synchronous
Min
4
5
ns
Asynchronous
0
t
WLAX
t
AH
Address Hold Time
(Notes 2, 3)
Synchronous
Min
6
7
ns
Asynchronous
20
20
t
AVDP
AVD# Low Time
Min
10
12
ns
t
DVWH
t
DS
Data Setup Time
Min
20
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
Min
0
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
20
30
ns
t
WHWL
t
WPH
Write Pulse Width High
Min
20
20
ns
t
SR/W
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 4)
Typ
9
μs
t
WHWH1
t
WHWH1
Accelerated Programming Operation (Note 4)
Typ
4
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Notes 4, 5)
Typ
0.2
sec
Chip Erase Operation (Notes 4, 5)
104
t
VID
V
ACC
Rise and Fall Time
Min
500
ns
t
VIDS
V
ACC
Setup Time (During Accelerated Programming)
Min
1
μs
t
VCS
V
CC
Setup Time
Min
50
μs
t
ELWL
t
CS
CE# Setup Time to WE#
Min
0
ns
t
AVSW
AVD# Setup Time to WE#
Min
4
5
ns
t
AVHW
AVD# Hold Time to WE#
Min
4
5
ns
t
ACS
Address Setup Time to CLK (Notes 2, 3)
Min
4
5
ns
t
ACH
Address Hold Time to CLK (Notes 2, 3)
Min
6
7
ns
t
AVHC
AVD# Hold Time to CLK
Min
4
5
ns
t
CSW
Clock Setup Time to WE#
Min
5
ns
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