參數(shù)資料
型號(hào)： AM49BDS640AHD8I
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA89
封裝： 10 X 8 MM, FBGA-89
文件頁數(shù)： 30/84頁
文件大?。?/td> 763K
代理商： AM49BDS640AHD8I
28
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
Read Mode Configuration
The device supports four different read modes: contin-
uous mode, and 8, 16, and 32 word linear wrap around
modes. A continuous sequence begins at the starting
address and advances the address pointer until the
burst operation is complete. If the highest address in
the device is reached during the continuous burst read
mode, the address pointer wraps around to the lowest
address.
For example, an eight-word linear read with wrap
around begins on the starting address written to the
device and then advances to the next 8 word boundary.
The address pointer then returns to the 1st word after
the previous eight word boundary, wrapping through
the starting location. The sixteen- and thirty-two linear
wrap around modes operate in a fashion similar to the
eight-word mode.
Table 13
shows the address bits and settings for the
four read modes.
Table 13.
Read Mode Settings
Note:
Upon power-up or hardware reset the default setting is
continuous.
Burst Active Clock Edge Configuration
By default, the device will deliver data on the rising
edge of the clock after the initial synchronous access
time. Subsequent outputs will also be on the following
rising edges, barring any delays. The device can be set
so that the falling clock edge is active for all synchro-
nous accesses. Address bit A17 determines this set-
ting; “1” for rising active, “0” for falling active.
RDY Configuration
By default, the device is set so that the RDY pin will
output V
OH
whenever there is valid data on the outputs.
The device can be set so that RDY goes active one
data cycle before active data. Address bit A18 deter-
mines this setting; “1” for RDY active with data, “0” for
RDY active one clock cycle before valid data. In asyn-
chronous mode, RDY is an open-drain output.
Configuration Register
Table 14
shows the address bits that determine the
configuration register settings for various device func-
tions.
Burst Modes
Address Bits
A16
A15
Continuous
0
0
8-word linear wrap around
0
1
16-word linear wrap around
1
0
32-word linear wrap around
1
1
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