參數(shù)資料
型號: AM42BDS640AGTD8IS
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-35 RoHS Compliant: No
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA93
封裝: 8 X 11.60 MM, FBGA-93
文件頁數(shù): 4/72頁
文件大小: 1060K
代理商: AM42BDS640AGTD8IS
November 1, 2002
Am42BDS640AG
3
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Flash Memory Simultaneous Operation Diagram 7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8
Special Package Handling Instructions ....................................8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
MCP Device Bus Operations. . . . . . . . . . . . . . . . 11
Table 1. Device Bus Operations..................................................... 12
Flash Device Bus Operations . . . . . . . . . . . . . . . 13
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................13
Requirements for Synchronous (Burst) Read Operation ........13
8-, 16-, and 32-Word Linear Burst with Wrap Around .........13
Table 2. Burst Address Groups .......................................................13
Burst Mode Configuration Register ........................................14
Reduced Wait-State Handshaking Option ..............................14
Simultaneous Read/Write Operations with Zero Latency .......14
Writing Commands/Command Sequences ............................14
Accelerated ProgramOperation ..........................................14
Autoselect Functions ...........................................................15
Standby Mode ........................................................................15
Automatic Sleep Mode ...........................................................15
RESET# Hardware Reset Input .............................................15
Output Disable Mode ..............................................................15
Hardware Data Protection ......................................................15
Write Protect (WP#) .............................................................16
Low V
CC
Write Inhibit ...........................................................16
Write Pulse “Glitch” Protection ............................................16
Logical Inhibit ......................................................................16
Power-Up Write Inhibit .........................................................16
Common Flash Memory Interface (CFI) . . . . . . .16
Table 3. CFI Query Identification String ..........................................16
SystemInterface String................................................................... 17
Table 5. Device Geometry Definition.............................................. 17
Table 6. Primary Vendor-Specific Extended Query ........................18
Table 7. Sector Address Table ........................................................19
Flash Command Definitions . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................23
Set Burst Mode Configuration Register Command Sequence 23
Figure 1. Synchronous/Asynchronous State Diagram.................... 23
Read Mode Setting ..............................................................23
Programmable Wait State Configuration .............................23
Table 8. Programmable Wait State Settings ...................................24
Handshaking Option ............................................................24
Table 9. Initial Access Codes ..........................................................24
Standard Handshaking Operation .......................................24
Table 10. Wait States for Standard Handshaking ...........................24
Burst Read Mode Configuration ..........................................24
Table 11. Burst Read Mode Settings ..............................................25
Burst Active Clock Edge Configuration ................................25
RDY Configuration ...............................................................25
Configuration Register ............................................................25
Table 12. Burst Mode Configuration Register .................................25
Sector Lock/Unlock Command Sequence ..............................25
Reset Command .....................................................................25
Autoselect Command Sequence ............................................26
Table 13. Device IDs ......................................................................26
ProgramCommand Sequence ...............................................26
Unlock Bypass Command Sequence ..................................27
Figure 2. Erase Operation.............................................................. 27
Chip Erase Command Sequence ...........................................27
Sector Erase Command Sequence ........................................28
Erase Suspend/Erase Resume Commands ...........................28
Figure 3. ProgramOperation......................................................... 29
Command Definitions .............................................................30
Table 14. Command Definitions ....................................................30
Flash Write Operation Status . . . . . . . . . . . . . . . 31
DQ7: Data#Polling .................................................................31
Figure 4. Data#Polling Algorithm.................................................. 31
RDY: Ready ............................................................................32
DQ6: Toggle Bit I ....................................................................32
Figure 5. Toggle Bit Algorithm....................................................... 32
DQ2: Toggle Bit II ...................................................................32
Table 15. DQ6 and DQ2 Indications ..............................................33
Reading Toggle Bits DQ6/DQ2 ...............................................33
DQ5: Exceeded Timng Limts ................................................33
DQ3: Sector Erase Timer .......................................................34
Table 16. Write Operation Status ...................................................34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 6. MaximumNegative OvershootWaveform...................... 35
Figure 7. MaximumPositive OvershootWaveform........................ 35
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 35
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 36
SRAM DC and Operating Characteristics . . . . . 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 8. Test Setup....................................................................... 38
Table 17. Test Specifications .........................................................38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
Figure 9. Input Waveforms and Measurement Levels................... 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
SRAMCE#s Timng ................................................................39
Figure 10. Timng Diagramfor Alternating
Between SRAMand Flash............................................................. 39
Synchronous/Burst Read ........................................................40
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK).......................................................................... 41
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock)..................................................................... 42
Figure 13. Synchronous Burst Mode Read.................................... 43
Figure 14. 8-word Linear Burst with Wrap Around......................... 43
Figure 15. Burst with RDY Set One Cycle Before Data................. 44
Figure 16. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Even Address.......................................................... 45
Figure 17. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address............................................................ 46
Asynchronous Read ...............................................................47
Figure 18. Asynchronous Mode Read with Latched Addresses.... 47
Figure 19. Asynchronous Mode Read............................................ 48
Figure 20. Reset Timngs............................................................... 49
Erase/ProgramOperations .....................................................50
Figure 21. Asynchronous ProgramOperation Timngs.................. 51
Figure 22. Alternate Asynchronous ProgramOperation Timngs... 52
Figure 23. Synchronous ProgramOperation Timngs.................... 53
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