參數(shù)資料
型號(hào)： AM42BDS640AGTC9IS
廠商： SPANSION LLC
元件分類(lèi)： 存儲(chǔ)器
英文描述： LJT 13C 13#22D PIN WALL RECP
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA93
封裝： 8 X 11.60 MM, FBGA-93
文件頁(yè)數(shù)： 24/72頁(yè)
文件大?。?/td> 1060K
代理商： AM42BDS640AGTC9IS
November 1, 2002
Am42BDS640AG
23
P R E L I M I N A R Y
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations.
Table 14, “Command Definitions,” on
page 30
defines the valid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence resets the
device to reading array data.
Refer to the AC Characteristics section for timing dia-
grams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read data
from any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the
“Erase Suspend/Erase Resume Commands” section
on page 28
section for more information.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the
“Reset
Command” section on page 25
section for more infor-
mation.
See also
“Requirements for Asynchronous Read Oper-
ation (Non-Burst)”
and
“Requirements for Synchronous
(Burst) Read Operation”
sections for more information.
The Asynchronous Read and Synchronous/Burst
Read tables provide the read parameters, and Figures
11
,
13
, and
18
show the timings.
Set Burst Mode Configuration Register
Command Sequence
The device uses a burst mode configuration register to
set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY con-
figuration, and synchronous mode active. The burst
mode configuration register must be set before the
device will enter burst mode.
The burst mode configuration register is loaded with a
three-cycle command sequence. The first two cycles
are standard unlock sequences. On the third cycle, the
data should be C0h, address bits A11–A0 should be
555h, and address bits A19–A12 set the code to be
latched. The device will power up or after a hardware
reset with the default setting, which is in asynchronous
mode. The register must be set before the device can
enter synchronous mode. The burst mode configura-
tion register can not be changed during device opera-
tions (program, erase, or sector lock).
Figure 1.
Synchronous/Asynchronous State
Diagram
Read Mode Setting
On power-up or hardware reset, the device is set to be
in asynchronous read mode. This setting allows the
system to enable or disable burst mode during system
operations. Address A19 determines this setting: “1’ for
asynchronous mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the
device of the number of clock cycles that must elapse
after AVD# is driven active before data will be available.
This value is determined by the input frequency of the
device. Address bits A14–A12 determine the setting
(see
Table 8
).
The wait state command sequence instructs the device
to set a particular number of clock cycles for the initial
access in burst mode. The number of wait states that
should be programmed into the device is directly
related to the clock frequency.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(A19 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(A19 = 1)
相關(guān)PDF資料
PDF描述
AM42BDS640AGTC9IT LJT 13C 13#22D SKT RECP
AM42BDS640AGTD8IS Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-35 RoHS Compliant: No
AM42BDS640AGTD8IT Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-35 RoHS Compliant: No
AM42BDS640AGBD8IS RES 93.1K-OHM 0.1% 0.125W 50PPM THIN-FILM SMD-1206 TR-7-PL ROHS
AM42BDS640AGBD8IT Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM42BDS640AGTC9IT 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
AM42BDS640AGTD8IS 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
AM42BDS640AGTD8IT 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
AM42BDS640AGTD9IS 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
AM42BDS640AGTD9IT 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
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