2-10 Revision 16 Power Consumption of Various Internal Resources Table 2-15 Different Componen" />
參數(shù)資料
型號: AGLP060V5-CSG289I
廠商: Microsemi SoC
文件頁數(shù): 52/134頁
文件大?。?/td> 0K
描述: IC FPGA IGLOO PLUS 60K 289-CSP
標準包裝: 152
系列: IGLOO PLUS
邏輯元件/單元數(shù): 1584
RAM 位總計: 18432
輸入/輸出數(shù): 157
門數(shù): 60000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 289-TFBGA,CSBGA
供應商設(shè)備封裝: 289-CSP(14x14)
IGLOO PLUS DC and Switching Characteristics
2-10
Revision 16
Power Consumption of Various Internal Resources
Table 2-15 Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device Specific Dynamic Power
(W/MHz)
AGLP125 AGLP060
AGLP030
PAC1
Clock contribution of a Global Rib
4.489
2.696
0.0001
PAC2
Clock contribution of a Global Spine
1.991
1.962
3.499
PAC3
Clock contribution of a VersaTile row
1.510
1.523
1.537
PAC4
Clock contribution of a VersaTile used as a sequential module
0.153
0.151
PAC5
First contribution of a VersaTile used as a sequential module
0.029
PAC6
Second contribution of a VersaTile used as a sequential module
0.323
PAC7
Contribution of a VersaTile used as a combinatorial module
0.280
0.300
0.278
PAC8
Average contribution of a routing net
1.097
1.081
1.130
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read operation
25.00
PAC12
Average contribution of a RAM block during a write operation
30.00
PAC13
Dynamic contribution for PLL
2.70
Note: 1. There is no Center Global Rib present in AGLP030, and thus it starts directly at the spine resulting in
0W/MHz.
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