參數(shù)資料
型號: ADV7441ABSTZ-5P
廠商: Analog Devices Inc
文件頁數(shù): 4/28頁
文件大?。?/td> 0K
描述: IC DECODER DIGITIZER 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Advantiv®
類型: 視頻解碼器
應(yīng)用: HDTV,投影儀,機頂盒
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
ADV7441A
Data Sheet
Rev. H | Page 12 of 28
Pin No.
Mnemonic
Type1
Description
107
TEST4
I/O
Test Pin. Do not connect.
77, 79, 81, 94, 96,
99, 76, 78, 80, 93,
95, 98
AIN1 to AIN12
I
Analog Video Input Channels.
24 to 33, 36 to 47,
52 to 55, 58 to 61
P0 to P29
O
Video Pixel Output Port.
19
INT1
O
Interrupt Signal. Can be active low or active high. The set of events that triggers an
interrupt is under user control.
20
SFL/SYNC_OUT/INT2
O
Subcarrier Frequency Lock (SFL). Contains a serial output stream that can be used to
lock the subcarrier frequency when this decoder is connected to any Analog Devices
digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available only in CP mode.
Interrupt Signal (INT2).
17
HS/CS
O
Horizontal Synchronization Output Signal (HS). Output by the SDP and CP.
Composite Synchronization (CS). A single signal containing both horizontal and
vertical synchronization pulses.
18
VS/FIELD
O
Vertical Synchronization Output Signal (VS). Output by the SDP and CP.
Field Synchronization Output Signal (FIELD). Field synchronization output signal in all
interlaced video modes.
16
DE/FIELD
O
Data Enable Signal (DE). Indicates active pixel data.
Field Synchronization Output Signal (FIELD). Field synchronization output signal in all
interlaced video modes.
11
SDA
I/O
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
12
SCL
I
I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for
the control port.
13
ALSB
I
This pin sets the second LSB of the slave address for each ADV7441A register map.
21
RESET
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7441A circuitry.
51
LLC
O
Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz.
65
XTAL1
O
This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an
external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In
crystal mode, the crystal must be a fundamental crystal.
66
XTAL
I
Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V
28.63636 MHz clock oscillator source to clock the ADV7441A.
70
ELPF
O
The recommended external loop filter must be connected to this ELPF pin.
102
AUDIO_ELPF
O
The recommended external loop filter must be connected to this AUDIO_ELPF pin.
85
REFOUT
O
Internal Voltage Reference Output.
86
CML
O
Common-Mode Level for the Internal ADCs.
90
REFN
O
Internal Voltage Reference Output.
92
REFP
O
Internal Voltage Reference Output.
63
HS_IN/CS_IN
I
HS Input Signal. Used in analog mode for 5-wire timing mode.
CS Input Signal. Used in analog mode for 4-wire timing mode.
For optimal performance, a 100 series resistor is recommended on the
HS_IN/CS_IN pin.
62
VS_IN
I
VS Input Signal. Used in analog mode for 5-wire timing mode. For optimal performance,
a 100 series resistor is recommended on the VS_IN pin.
75
SOG
I
Synchronization-on-Green Input. This pin is used in embedded synchronization mode.
97
SOY
I
Synchronization-on-Luma Input. This pin is used in embedded synchronization mode.
112
RXA_CN
I
Digital Input Clock Complement of Port A in the HDMI Interface.
113
RXA_CP
I
Digital Input Clock True of Port A in the HDMI Interface.
115
RXA_0N
I
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
116
RXA_0P
I
Digital Input Channel 0 True of Port A in the HDMI Interface.
118
RXA_1N
I
Digital Input Channel 1 Complement of Port A in the HDMI Interface.
119
RXA_1P
I
Digital Input Channel 1 True of Port A in the HDMI Interface.
121
RXA_2N
I
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
122
RXA_2P
I
Digital Input Channel 2 True of Port A in the HDMI Interface.
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