參數(shù)資料
型號: ADV7202
廠商: Analog Devices, Inc.
元件分類: Codec
英文描述: Simultaneous Sampling Video Rate Codec
中文描述: 同時(shí)采樣率視頻編解碼器
文件頁數(shù): 4/26頁
文件大?。?/td> 216K
代理商: ADV7202
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202–SPECIFICATIONS
5 V SPECIFICATIONS
(AVDD/DVDD = 4.75 – 5.25, V
REF
= 1.235 V R
SET
= 1.2 k , all specifications T
MIN
to T
MAX1
unless otherwise noted.)
–4–
Parameter
Min
Typ
Max
Unit
Condition
2
PROGRAMMABLE GAIN
AMPLIFIER
Video ADC Gain
CLAMP CIRCUITRY
3
Clamp Off Leakage Current
Clamp Fine Source/Sink Current
Clamp Coarse Source/Sink Current
CLOCK CONTROL
4
DACCLK0/1
6, 7
DACCLK1
DACCLK1
8
Data Setup Time, t
12
Data Hold Time, t
13
Pipeline Delay
5
, t
18
Video ADC
SAR
–6
+6
dB
Setup Conditions
TBD
μ
A
μ
A
mA
3
0.5
27
80
27
2
2
MHz
MHz
MHz
ns
ns
Dual CLK Dual Edge Mode
Single Edge Single Clock Mode
4:2:2 Mode
All Input Modes
TBD
TBD
Clock Cycles
Clock Cycles
RESET CONTROL
RESET
Low Time
10
ns
NOTES
1
Temperature range T
to T
: 0
o
C to 70
o
C.
2
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
3
External clamp capacitor = 0.1
μ
F.
4
TTL input values are 0 V to 3 V, with input rise/fall times
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load
10 pF.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
6
Maximum clock speed determined by setup and hold conditions.
7
Single DAC only.
8
Guaranteed by Characterization.
Specifications subject to change without notice.
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