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參數(shù)資料
| 型號： | ADV7202 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Simultaneous Sampling Video Rate Codec |
| 中文描述： | 同時采樣率視頻編解碼器 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 216K |
| 代理商： | ADV7202 |
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REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–20–
CLAMP REGISTER 0
CR0 (CR00–CR07)
(Address (SR4–SR0) = 06H)
Figure 25 shows the various operations under the control of
Clamp Register 0.
CR0 BIT DESCRIPTION
Clamp Level/4 (CR00–CR07)
In order to perform an accurate AGC gain operation, it is
necessary to know to what level the user is clamping the black
level. This black level is then subtracted from the 10-bit ADC
output before gaining. It is then added on again afterwards. It
should be noted that this register is eight bit and will hold the
value of Clamp Value/4.
CLAMP REGISTER 1
CR1 (CR10–CR17)
(Address (SR4–SR0) = 07H)
Figure 26 shows the various operations under the control of
Clamp Register 1.
CR1 BIT DESCRIPTION
Fine Clamp On Time (CR10–CR12)
There are three fine clamp circuits on the chip. This I
2
C/SPI
word controls the number of clock cycles for which the fine
clamps are switched on per video line. The clamp is switched on
after a SYNC pulse is received on the SYNC_IN pin, provided
the relevant enabling bit is set (see CR16).
Coarse Clamp On Time (CR13–CR15)
There are three coarse clamp circuits on the chip. This I
2
C
word controls the number of clock cycles for which the fine
clamps are switched on per video line. The clamp is switched on
after a SYNC pulse is received on the SYNC_IN pin, provided
the relevant enabling bit is set (see CR16).
Synchronize Clamps (CR16)
Setting this bit to “1” forces the clamps to wait until the next
sync pulse before switching on.
Reserved (CR17)
Zero must be written to this bit.
CR07
CR02
CR04
CR06
8-BIT [7:0] CLAMP
LEVEL, CR00 HOLDS THE
LSB, CR07 THE MSB
CR07
–
CR00
CR05
CR03
CR01
CR00
CLAMP LEVEL
Figure 25. Clamp Register 0
CR11
CR17
CR12
CR14
CR15
CR13
CR10
CR16
CR16
0
1
OFF
ON
SYNCHRONIZE
CLAMPS
ZERO MUST BE
WRITTEN TO
THIS BIT
CR17
CR12 CR11 CR10
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
2 CLOCK CYCLES
4 CLOCK CYCLES
8 CLOCK CYCLES
16 CLOCK CYCLES
32 CLOCK CYCLES
64 CLOCK CYCLES
128 CLOCK CYCLES
256 CLOCK CYCLES
FINE CLAMP ON TIME
CR15 CR14 CR13
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
2 CLOCK CYCLES
4 CLOCK CYCLES
8 CLOCK CYCLES
16 CLOCK CYCLES
32 CLOCK CYCLES
64 CLOCK CYCLES
128 CLOCK CYCLES
256 CLOCK CYCLES
COARSE CLAMP ON TIME
Figure 26. Clamp Register 1
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