參數(shù)資料
型號： ADV7202
廠商： Analog Devices, Inc.
元件分類： Codec
英文描述： Simultaneous Sampling Video Rate Codec
中文描述： 同時采樣率視頻編解碼器
文件頁數(shù)： 18/26頁
文件大?。?/td> 216K
代理商： ADV7202
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–18–
MODE REGISTER 2
MR2 (MR20–MR27)
(Address (SR4–SR0) = 02H)
Figure 22 shows the various operations under the control of
Mode Register 2.
MR1 BIT DESCRIPTION
Analog Input Configuration (MR20–MR23)
This control selects the analog input configuration, up to six
CVBS input channels, or two component YUV, or three S-Video
and eight auxiliary inputs. See Figure 22 for details.
SHA0 Control (MR24)
Setting this bit to “0” enables SHA0; otherwise, this SHA is
powered down (SHA = Sample and Hold Amplifier).
SHA1 Control (MR25)
Setting this bit to “0” enables SHA1; otherwise, this SHA is
powered down.
SHA2 Control (MR26)
Setting this bit to “0” enables SHA2; otherwise, this SHA is
powered down.
AUX Control (MR27)
Setting this bit to “0” enables the auxiliary ADC; otherwise, this
Aux ADC is powered down.
ANALOG INPUT CONFIGURATION
*
MR23 MR22 MR21 MR20
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
CVBS IN ON AIN1
CVBS IN ON AIN2
CVBS IN ON AIN3
RESERVED
CVBS IN ON AIN5
CVBS IN ON AIN6
Y/C IN ON AIN1, AIN4
Y/C IN ON AIN2, AIN3
YUV IN ON AIN2, AIN3, AIN6
CVBS IN ON AIN1, 8 AUX INPUTS
CVBS IN ON AIN2, 8 AUX INPUTS
MR21
MR27
MR22
MR24
MR26
MR23
MR20
MR25
MR26
0
1
NORMAL
POWER-DOWN
SHA2 CONTROL
MR27
0
1
NORMAL
POWER-DOWN
AUX CONTROL
MR25
0
1
NORMAL
POWER-DOWN
SHA1 CONTROL
MR24
0
1
NORMAL
POWER-DOWN
SHA0 CONTROL
*
SEE FIGURE : XX
Figure 22. Mode Register 2
MODE REGISTER 3
MR3 (MR30–MR37)
(Address (SR4–SR0) = 03H)
Figure 23 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Clamp Current (MR30)
Setting this bit to “1” enables the doubling of all clamp currents.
Analog Input Mode (MR31)
Setting this bit to “1” enables differential mode for the analog
inputs; otherwise, the inputs are single ended. See Figure 23.
SHA Gain (MR32)
Setting this bit to “0” enables SHA gain of 1. If the bit is set to
“1,” the SHA gain is 2. The SHA gain will limit the input signal
range, see Figure 23.
Voltage Clamp (MR33)
Setting this bit to “1” will enable the voltage clamps.
Output Enable (MR34)
Setting this bit to “1” puts the digital outputs into high im-
pedance.
SYNC Polarity (MR35)
This bit controls the polarity of the SYNC_IN pin. If the bit
is set to “0,” a logic low pulse corresponds to H-Sync. If the bit
is “1,” a logic high pulse corresponds to H-Sync. This sync in
pulse can then be used to control the synchronization of AGC/
Clamping, see AR12.
Reserved (MR36–MR37)
Zero must be written to both these registers.
MR37
MR32
MR34
MR36
MR34
0
1
NORMAL
HIGH Z
OUTPUT ENABLE
MR35
MR35
0
1
LOW
HIGH
SYNC POLARITY
MR33
MR31
MR30
MR33
0
1
OFF
ON
VOLTAGE CLAMP
MR32
0
1
1
2
SHA GAIN
MR30
0
1
NORMAL
DOUBLE
CLAMP CURRENT
MR31
0
1
SINGLE-ENDED
POWER-DOWN
ANALOG INPUT
MR36
–
MR37
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
Figure 23. Mode Register 3
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ADV7280ABCPZ-M-RL 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標準包裝:5,000
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