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參數(shù)資料
型號(hào)： ADV7179KCPZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 50/52頁(yè)
文件大?。?/td> 0K
描述： IC ENCODER VID NTSC/PAL 40LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
電壓 - 電源，模擬： 2.8 V，3.3 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 786 (CN2011-ZH PDF)
其它名稱： ADV7179KCPZ-REELDKR
ADV7174/ADV7179
Rev. B | Page 7 of 52
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 4.
Parameter
Min
Typ
Max
Unit
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulse Width, t1
0.6
μs
SCLOCK Low Pulse Width, t2
1.3
μs
Hold Time (Start Condition), t3
After this period, the first clock is generated
0.6
μs
Setup Time (Start Condition), t4
Relevant for repeated start condition
0.6
μs
Data Setup Time, t5
100
ns
SDATA, SCLOCK Rise Time, t6
300
ns
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
μs
ANALOG OUTPUTS3, 5
Analog Output Delay
7
ns
DAC Analog Output Skew
0
ns
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
3.5
ns
Data Hold Time, t12
4
ns
Control Setup Time, t11
4
ns
Control Hold Time, t12
3
ns
Digital Output Access Time, t13
12
ns
Digital Output Hold Time, t14
8
ns
Pipeline Delay, tPD6
48
Clock Cycles
TELETEXT3, 4
Digital Output Access Time, t16
23
ns
Data Setup Time, t17
2
ns
Data Hold Time, t18
6
ns
RESET Low Time
6
ns
1 The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range.
2 Temperature range TMIN to TMAX: –40°C to +85°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4 Guaranteed by characterization.
5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
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