參數(shù)資料
型號： ADV7179KCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 31/52頁
文件大?。?/td> 0K
描述： IC ENCODER VID NTSC/PAL 40LFCSP
標準包裝： 1
類型： 視頻編碼器
應用： 數(shù)碼相機，手機，便攜式視頻
電壓 - 電源，模擬： 2.8 V，3.3 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應商設備封裝： 40-LFCSP-VQ（6x6）
包裝： 標準包裝
產品目錄頁面： 786 (CN2011-ZH PDF)
其它名稱： ADV7179KCPZ-REELDKR
ADV7174/ADV7179
Rev. B | Page 37 of 52
TELETEXT REQUEST CONTROL REGISTER (TC07)
Bits:
TC07–TC00
Address:
SR4–SR0 = 19H
Teletext control register is an 8-bit-wide register (see Figure 50).
Table 17. Teletext Request Control Register
Bit Name
Bit No.
Description
TTXREQ Rising Edge Control
TC07–TC04
These bits control the position of the rising edge of TTXREQ. It can be
programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see
TTXREQ Falling Edge Control
TC03–TC00
These bits control the position of the falling edge of TTXREQ. It can be
programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls
the active window for Teletext data. Increasing this value reduces the amount of
Teletext bits below the default of 360. If Bits TC03–TC00 are 00H when Bits TC07–
TC04 are changed, the falling edge of TTXREQ tracks that of the rising edge, i.e.,
the time between the falling and rising edge remains constant (see Figure 49).
CGMS_WSS REGISTER 0 (C/W0)
Bits:
C/W07–C/W00
Address:
SR4–SR0 = 16H
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register.
TC01
TC00
TC07
TC02
TC04
TC03
TC05
TC06
TTXREQ RISING EDGE CONTROL
TC07 TC06
TC05 TC04
00
0
00 PCLK
00
0
1
11
1
11
1
0
""
"
1PCLK
"PCLK
14 PCLK
15 PCLK
TTXREQ FALLING EDGE CONTROL
TC03 TC02
TC01 TC00
0PCLK
1PCLK
"PCLK
14 PCLK
15 PCLK
00
0
00
0
1
11
1
11
1
0
""
"
02980-A
-049
Figure 50. Teletext Control Register
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
C/W07
WIDE SCREEN
SIGNAL CONTROL
0
DISABLE
1
ENABLE
0
DISABLE
1
ENABLE
C/W05
CGMS ODD FIELD
CONTROL
C/W06
CGMS EVEN FIELD
CONTROL
0
DISABLE
1
ENABLE
C/W04
CGMS CRC CHECK
CONTROL
0
DISABLE
1
ENABLE
C/W03 – C/W00
CGMS DATA BITS
02980-A
-050
Figure 51. CGMS_WSS Register 0
Table 18. C/W0 Bit Description
Bit Name
Bit No.
Description
CGMS Data Bits
C/W03–C/W00
These four data bits are the final four bits of the CGMS data output stream. Note it is
CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.
CGMS CRC Check Con
trol
C/W04
When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check
sequence, are calculated internally by the ADV7174/ADV7179. If this bit is disabled (0), the
CRC values in the register are output to the CGMS data stream.
CGMS Odd Field Control
C/W05
When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode.
CGMS Even Field Control
C/W06
When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode.
WSS Control
C/W07
When this bit is set (1), wide screen signaling is enabled. Note this is only valid in PAL mode.
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