參數(shù)資料
型號： ADV7179KCPZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 25/52頁
文件大?。?/td> 0K
描述： IC ENCODER VID NTSC/PAL 40LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： 數(shù)碼相機，手機，便攜式視頻
電壓 - 電源，模擬： 2.8 V，3.3 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 786 (CN2011-ZH PDF)
其它名稱： ADV7179KCPZ-REELDKR
ADV7174/ADV7179
Rev. B | Page 31 of 52
MODE REGISTER 3 (MR3)
Bits:
MR37–MR30
Address:
SR4–SR0 = 03H
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3.
MR31
MR30
MR37
MR32
MR34
MR33
MR35
MR36
MR30
MR31
RESERVED
VBI_OPEN
0
DISABLE
1
ENABLE
MR32
DAC OUTPUT
0
COMPOSITE
1
GREEN/LUMA/Y
MR33
DAC A
BLUE/COMP/Pb
DAC B
RED/CHROMA/Pr
DAC C
CHROMA OUTPUT
SELECT
0
DISABLE
1
ENABLE
MR34
TELETEXT
ENABLE
0
DISABLE
1
ENABLE
MR35
TTXREQ BIT
MODE CONTROL
0
NORMAL
1
BIT REQUEST
MR36
INPUT DEFAULT
COLOR
0
DISABLE
1
ENABLE
MR37
02980-A
-040
Figure 41. Mode Register 3
Table 12. MR3 Bit Description
Bit Name
Bit No.
Description
Revision Code
MR30–MR31
These bits are read-only and indicate the revision of the device.
VBI Open
MR32
This bit determines whether or not data in the vertical blanking interval (VBI) is output to
the analog outputs or blanked. VBI data insertion is not available in Slave Mode 0. Also,
when both BLANK input control and VBI open are enabled, BLANK input control has
priority, i.e., VBI data insertion will not work.
DAC Output
MR33
This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A
complete list of all DAC output configurations is shown in Table 13.
Chroma Output Select
MR34
With this active high bit it is possible to output an extra chrominance signal C, on DAC A
in any configuration that features a CVBS signal.
Teletext Enable
MR35
This bit must be set to 1 to enable Teletext data insertion on the TTX pin.
TTXREQ Bit Mode Control
MR36
This bit enables switching of the Teletext request signal from a continuous high signal
(MR36 = 0) to a bitwise request signal (MR36 = 1).
Input Default Color
MR37
This bit determines the default output color from the DACs for zero input pixel data (or
disconnected). A Logic 0 means that the color corresponding to 00000000 is displayed. A
Logic 1 forces the output color to black for 00000000 pixel input video data.
Table 13. DAC Output Configuration Matrix
MR34
MR40
MR41
MR33
DAC A
DAC B
DAC C
0
CVBS
C
CVBS: Composite Video Baseband Signal
Y: Luminance Component Signal (For YPbPr or Y/C Mode)
C: Chrominance Signal (For Y/C Mode)
Pb: ColorComponent Signal (For YPbPr Mode)
Pr: Color Component Signal (For YPbPr Mode)
R: RED Component Video (For RGB Mode)
G: GREEN Component Video (For RGB Mode)
B: BLUE Component Video (For RGB Mode)
Each DAC can be powered on or off individually
See MR1 Description and Figure 39.
0
1
Y
CVBS
C
0
1
0
CVBS
C
0
1
Y
CVBS
C
0
1
0
CVBS
B
R
0
1
0
1
G
B
R
0
1
0
CVBS
Pb
Pr
0
1
Y
Pb
Pr
1
0
C
CVBS
C
1
0
1
Y
CVBS
C
1
0
1
0
C
CVBS
C
1
0
1
Y
CVBS
C
1
0
C
B
R
1
0
1
G
B
R
1
0
C
Pb
Pr
1
Y
Pb
Pr
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