參數(shù)資料
型號(hào): ADV7176A*
廠商: Analog Devices, Inc.
英文描述: High Quality. 10-Bit. Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 較高的質(zhì)量。 10位。數(shù)字無線電咨詢委員會(huì)- 601的PAL / NTSC制式視頻編碼器
文件頁數(shù): 24/52頁
文件大?。?/td> 629K
ADV7175A/ADV7176A
–24–
REV. B
MODE RE GIST E R 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 33 shows the various operations under the control of Mode
Register 1. T his register can be read from as well as written to.
MR1 BIT DE SCRIPT ION
Interlaced Mode Control (MR10)
T his bit is used to set up the output to interlaced or noninter-
laced mode. T his mode is only relevant when the part is in
composite video mode.
Closed Captioning Field Control (MR12–MR11)
T hese bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
DAC Control (MR16–MR13)
T hese bits can be used to power down the DACs. T his can
be used to reduce the power consumption of the ADV7175A/
ADV7176A if any of the DACs are not required in the application.
Color Bar Control (MR17)
T his bit can be used to generate and output an internal color
bar test pattern. T he color bar configuration is 75/7.5/75/7.5
for NT SC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7175A/ADV7176A is
configured in a master timing mode as per the one selected by
bits T R01 and T R02.
SUBCARRIE R FRE QUE NCY RE GIST E R 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)
T hese 8-bit wide registers are used to set up the subcarrier fre-
quency. T he value of these registers are calculated by using the
following equation:
Subcarrier Frequency Register =
2
32
±1
F
CLK
×
F
SCF
i.e.: NT SC Mode,
F
CLK
= 27 MHz,
F
SCF
= 3.5795454 MHz
Subcarrier Frequency Value =
2
32
±1
27
×
10
6
×
3.5795454
×
10
6
= 21F07C16
HEX
Figure 34 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 3
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 0
FSC30
FSC29
FSC27
FSC25
FSC28
FSC24
FSC31
FSC26
FSC22
FSC21
FSC19
FSC17
FSC20
FSC16
FSC23
FSC18
FSC14
FSC13
FSC11
FSC9
FSC12
FSC8
FSC15
FSC10
FSC6
FSC5
FSC3
FSC1
FSC4
FSC0
FSC7
FSC2
Figure 34. Subcarrier Frequency Register
SUBCARRIE R PHASE RE GIST E R (FP7–FP0)
(Address [SR4–SR0] = 06H)
T his 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41
°
.
T IMING RE GIST E R 0 (T R07–T R00)
(Address [SR4–SR0] = 07H)
Figure 35 shows the various operations under the control of
T iming Register 0. T his register can be read from as well as
written to. T his register can be used to adjust the width and
position of the master mode timing signals.
T R0 BIT DE SCRIPT ION
Master/Slave Control (T R00)
T his bit controls whether the ADV7175A/ADV7176A is in
master or slave mode.
T iming Mode Control (T R02–T R01)
T hese bits control the timing mode of the AD V7175A/
ADV7176A. T hese modes are described in the T iming and
Control section of the data sheet.
BLANK
Control (T R03)
T his bit controls whether the
BLANK
input is used when the
part is in slave mode.
Luma Delay Control (T R05–T R04)
T hese bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Select (T R06)
T his bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
T iming Register Reset (T R07)
T oggling T R07 from low to high and low again resets the inter-
nal timing counters. T his bit should be toggled after power-up,
reset or changing to a new timing mode.
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLACK INPUT
CONTROL
0
1
ENABLE
DISABLE
TR03
PIXEL PORT
CONTROL
TR06
0
1
8-BIT
16-BIT
MASTER/SLAVE
CONTROL
TR00
0
1
SLAVE TIMING
MASTER TIMING
LUMA DELAY
0
0
1
1
0
1
0
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TR05 TR04
TIMING MODE
SELECTION
TR02 TR01
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
Figure 35. Timing Register 0
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