參數(shù)資料
型號: ADV7176A*
廠商: Analog Devices, Inc.
英文描述: High Quality. 10-Bit. Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 較高的質(zhì)量。 10位。數(shù)字無線電咨詢委員會- 601的PAL / NTSC制式視頻編碼器
文件頁數(shù): 10/52頁
文件大?。?/td> 629K
ADV7175A/ADV7176A
–10–
REV. B
PIN FUNCT ION DE SCRIPT IONS
Pin
No.
Input/
Output
Mnemonic
Function
1, 11, 20,
28, 30
10, 19, 21,
29, 43
15
V
AA
P
Power Supply (+3 V to +5 V).
GND
HSYNC
G
I/O
Ground Pin.
HSYNC
(Modes 1 and 2) Control Signal. T his pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and
VSYNC
(Mode 2) Control Signal. T his
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
Video Blanking Control Signal. T he pixel inputs are ignored when this is
logic level “0.” T his signal is optional.
T T L Address Input. T his signal sets up the LSB of the MPU address.
T he input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. T his is NT SC operation, T iming Slave Mode
0, 8-bit operation, 2
×
composite and S-Video out and all DACs powered on.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1
μ
F capacitor from COMP to V
AA
. For
Optimum Dynamic Performance in L ow Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
PAL/NT SC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NT SC and 1300 mV for PAL.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150
resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
T his pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high
to low transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real T ime Control (RT C) input.
T eletext Data Request Signal/Defaults to GND when T eletext not selected
(enables backward compatibility to ADV7175/ADV7176).
T eletext Data/Defaults to V
AA
when T eletext not selected (enables backward
compatibility to ADV7175/ADV7176).
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
T T L Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.52 MHz (NT SC) or 29.5 MHz (PAL) can be
used for square pixel operation.
16
FIELD/
VSYNC
I/O
17
BLANK
I/O
18
22
ALSB
RESET
I
I
23
24
25
SCLOCK
SDAT A
COMP
I
I/O
O
26
27
31
32
DAC C
DAC D
DAC B
DAC A
O
O
O
O
33
34
V
REF
R
SET
I/O
I
35
SCRESET /RT C
I
36
T T X REQ/GND
O
37
T T X /V
AA
I
38–42
2–9, 12–14
44
P0–P15
I
CLOCK
I
相關(guān)PDF資料
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