- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374046 > ADV7175 (Analog Devices, Inc.) Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder PDF資料下載
參數(shù)資料
| 型號： | ADV7175 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| 中文描述： | 綜合數(shù)字無線電咨詢委員會，601 YCrCb到PAL / NTSC制式視頻編碼器 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 447K |
| 代理商： | ADV7175 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AC CHARACT E RIST ICS
1
Parameter
Min
T yp
Max
Units
Condition
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma Nonlinear Phase
Chroma/Luma Intermod
Chroma/Luma Intermod
Chroma/Luma Gain Ineq
Chroma/Luma Delay Ineq
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
0.6
1
1.7
0.2
0.4
0.6
1
0.8
60
59
±
%
±°
±°
±
%
±
%
±
%
ns
±
%
dB
dB
Referenced to 40 IRE
NT SC
PAL
Referenced to 714 mV (NT SC)
Referenced to 700 mV (PAL)
TIMNG–SPECIFICATIONS
2
Parameter
Min
T yp
Max
Units
Condition
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulse Width, t
1
SCLOCK Low Pulse Width, t
2
Hold T ime (Start Condition), t
3
Setup T ime (Start Condition), t
4
Data Setup T ime, t
5
SDAT A, SCLOCK Rise T ime, t
6
SDAT A, SCLOCK Fall T ime, t
7
Setup T ime (Stop Condition), t
8
ANALOG OUT PUT S
1, 5
Analog Output Delay
DAC Analog Output Skew
0
4.0
4.7
4.0
4.7
250
100
kHz
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
After this period the first clock pulse is generated
Relevant for repeated start condition.
1
300
4.7
5
0
ns
ns
C
LOCK CONT ROL
AND PIX EL PORT
6
F
CLOCK
Clock High T ime t
9
Clock Low T ime t
10
Data Setup T ime t
11
Data Hold T ime t
12
Control Setup T ime t
11
Control Hold T ime t
12
Digital Output Access T ime t
13
Digital Output Hold T ime t
14
Pipeline Delay t
15
24.52 27
8
8
3.5
1
4
2
29.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
24
6
37
NOT ES
1
Guaranteed by characterization.
2
T T L input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. Analog Output Load
≤
3 pF.
3
±
5% for all versions.
4
T emperature range (T
MIN
to T
MAX
); 0
°
C to +70
°
C.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following inputs:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC,
FIELD/
VSYNC, BLANK
Clock Input:
CLOCK
Specifications subject to change without notice.
ADV7175/ADV7176
REV. A
–3–
(V
AA
= +5 V
3
, V
REF
= 1.235 V R
SET
= 150
V
. All specifications T
MN
to T
MAX4
unless otherwse noted)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7175KS | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| ADV7176 | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| ADV7176KS | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| ADV7177KS | Integrated Digital CCIR-601 to PAL/NTSC Video Encoder |
| ADV7177 | Integrated Digital CCIR-601 to PAL/NTSC Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7175A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder |
| ADV7175AKS | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder |
| ADV7175KS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| ADV7176 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| ADV7176A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。