參數(shù)資料
型號： ADV7175
廠商： Analog Devices, Inc.
英文描述： Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
中文描述： 綜合數(shù)字無線電咨詢委員會，601 YCrCb到PAL / NTSC制式視頻編碼器
文件頁數(shù)： 21/36頁
文件大小： 447K
代理商： ADV7175
ADV7175/ADV7176
REV. A
–21–
MR21
MR27
MR22
MR23
MR26
MR25
MR24
MR20
CHROMINANCE
CONTROL
MR24
0
1
ENABLE COLOR
DISABLE COLOR
GENLOCK SELECTION
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
1
1
MR22 MR21
RGB/YUV
CONTROL
MR26
0
1
RGB OUTPUT
YUV OUTPUT
SQUARE PIXEL
CONTROL
MR20
0
1
DISABLE
ENABLE
BURST
CONTROL
0
1
ENABLE BURST
DISABLE BURST
MR25
LOWER POWER
MODE
MR27
0
1
DISABLE
ENABLE
CCIR624/CCIR601
CONTROL
MR23
0
1
CCIR624 OUTPUT
CCIR601 OUTPUT
Figure 38. Mode Register 2
MR31
MR37
MR32
MR33
MR36
MR35
MR34
MR30
DAC OUTPUT
SWITCHING
DAC B
MR37
0
1
DAC A
COMPOSITE
GREEN/LUMA/Y
BLUE/COMP/U
BLUE/COMP/U
DAC C
RED/CHROMA/V
RED/CHROMA/V
DAC D
GREEN/LUMA/Y
COMPOSITE
MR36-MR30
(RESERVED)
ZERO SHOULD BE
WRITTEN TO THESE BITS
Figure 40. Mode Register 3
CCIR624/CCIR601 Control (MR23)
T his bit switches the video output between CCIR624 and
CCIR601 video standard.
Chrominance Control (MR24)
T his bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
T his bit enables the burst information to be switched on and off
the video output.
RGB/Y UV Control (MR26)
T his bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Lower Power Control (MR27)
T his bit enables the lower power mode of the ADV7175/
ADV7176.
NT SC PE DE ST AL CONT ROL RE GIST E RS 3–0
(PCE 15–0, PCO15–0)
(Subaddress (SR4–SR0) = 11-0E H)
T hese 8-bit wide registers are used to set up the NT SC pedestal
on a line by line basis in the vertical blanking interval for both
odd and even fields. Figure 39 shows the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal off on the equivalent line.
FIELD 1/3
PCO6
PCO5
PCO3
PCO1
PCO4
PCO2
PCO0
PCO7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO14
PCO13
PCO11
PCO9
PCO12
PCO10
PCO8
PCO15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
FIELD 2/4
PCE6
PCE5
PCE3
PCE1
PCE4
PCE2
PCE0
PCE7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE14
PCE13
PCE11
PCE9
PCE12
PCE10
PCE8
PCE15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
Figure 39. Pedestal Control Registers
MODE RE GIST E R 3 MR3 (MR37–30)
(Address (SR4–SR0) = 12H)
Mode Register 3 is an 8-bit wide register.
Figure 34 shows the various operations under the control of
Mode Register 3. Bits MR36–MR30 are reserved and Logic “0”
should be written to them.
MODE RE GIST E R 3 (MR37–MR30) DE SCRIPT ION
DAC Switching Control (MR37)
T his bit is used to switch the luminance signal onto the compos-
ite DAC. Figure 40 illustrates the DAC outputs and how they
switch when MR 37 is set to Logic “1”.
相關(guān)PDF資料
PDF描述
ADV7175KS Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176 Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176KS Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7177KS Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7177 Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7175A 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7175AKS 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7175KS 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176A 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
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