![](http://datasheet.mmic.net.cn/310000/ADV7160_datasheet_16243892/ADV7160_4.png)
REV. 0
–4–
ADV7160/ADV7162
MPU P
ORT
8,9
Parameter
220 MHz
Version
170 MHz
Version
140 MHz
Version
Units
Conditions/Comments
t
19
t
20
t
21
t
t
22
t
249
t
259
t
269
t
27
t
28
0
10
45
25
5
45
20
5
20
5
0
10
45
25
5
45
20
5
20
5
0
10
45
25
5
45
20
5
20
5
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
R
/W
, C0, C1 to
CE
Setup Time
R
/W
, C0, C1 to
CE
Hold Time
CE
Low Time
CE
High Time
CE
Asserted to Data-Bus Driven
CE
Asserted to Data Valid
CE
Disabled to Data-Bus Three-Stated
CE
Disabled to Data Invalid
Write Data (D0–D9) Setup Time
Write Data (D0–D9) Hold Time
NOTES
General Notes
1
TTL input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points.
ECL inputs (CLOCK,
CLOCK
) are V
–0.8 V to V
AA
–1.8 V, with input rise/fall times
≤
2 ns, measured between the 10% and 90% points.
Timing reference points at 50% for inputs and outputs.
Analog output load
≤
10 pF.
Data-Bus (D0–D9) loaded as shown in Figure 1.
Digital output load for LOADOUT, PRGCKOUT & SCKOUT
≤
30 pF.
2
±
5% for all versions
3
Temperature range (T
MIN
to T
MAX
); 0
°
C to +70
°
C.
Notes on PIXEL PORT
4
Pixel Port consists of the following inputs:
Pixel Inputs:
RED [A, B, C, D]
GREEN [A, B, C, D]
Palette Selects:
PS0 [A, B, C, D];
PS1[A, B, C, D]
Pixel Controls:
SYNC
,
BLANK
,
TRISYNC
, ODD/
EVEN
Clock Inputs:
CLOCK,
CLOCK
, LOADIN, SCKIN
Clock Outputs:
LOADOUT, PRGCKOUT, SCKOUT
5
τ
is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode:
2:1 multiplexing;
τ
= CLOCK
×
2
= 2
×
t
1
ns
4:1 multiplexing;
τ
= CLOCK
×
4
= 4
×
t
1
ns
8:1 multiplexing;
τ
= CLOCK
×
8
= 8
×
t
ns
6
These fixed values for Pipeline Delay are valid under conditions where t
10
and
τ
-t
11
are met. If either t
10
or
τ
-t
11
are not met, the part will operate but the Pipeline
Delay is increased.
Notes on ANALOG OUTPUTS
7
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Output rise/fall time measured between the 10% and 90% points of full-scale transition.
Transition time measured from the 50% point of full scale transition to the output remaining within 2% of the final output value. (Transition time does not include
clock and data feedthrough).
Notes on MPU PORT
8
t
23
and t
24
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
9
t
and t
are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured numbers are
then extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the times t
25
and t
26
, quoted in the Timing Characteristics are the
true values for the device and as such are independent of external loading capacitances.
Specifications subject to change without notice.
BLUE [A, B, C, D]
100pF
TO OUTPUT
PIN
I
SOURCE
I
SINK
+2.1V
Figure 1. Load Circuit for Databus Access and Relinquish Times