參數(shù)資料
型號： ADV7150
廠商： Analog Devices, Inc.
英文描述： CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC(三通道,10位視頻RAM-D/A轉(zhuǎn)換器)
中文描述： 220兆赫的CMOS真彩色圖形三路10位顯存，數(shù)模轉(zhuǎn)換器（三通道，10位視頻RAM的的D / A轉(zhuǎn)換器）
文件頁數(shù)： 4/36頁
文件大?。?/td> 434K
代理商： ADV7150
ADV7150
–4–
REV. A
NOT ES
1
T T L input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK ,
CLOCK
) are
V
–0.8 V to V
–1.8 V, with input rise/fall times
≤
2 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and out-
puts. Analog output load
≤
10 pF. Databus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT , PRGCK OUT , SCK OUT , I
PLL
and
SYNCOUT
≤
30 pF.
2
±
5% for all versions.
3
T emperature range (T
to T
): 0
°
C to +70
°
C; T
(Silicon Junction T emperature)
≤
100
°
C.
4
Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B, C, D]; GREEN [A, B, C, D]; BLUE [A, B, C, D], Palette Selects: PS0 [A, B, C, D]; PS1
[A, B, C, D]; Pixel Controls:
SYNC
,
BLANK
; Clock Inputs: CLOCK ,
CLOCK
, LOADIN, SCK IN; Clock Outputs: LOADOUT , PRGCK OUT , SCK OUT .
5
τ
is the LOADOUT Cycle T ime and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing;
τ
= CLOCK = t
1
ns. 2:1 Multi-
plexing;
τ
= CLOCK
×
2 = 2
×
t
ns. 4:1 Multiplexing;
τ
= CLOCK
×
4 = 4
×
t
1
ns.
6
T hese fixed values for Pipeline Delay are valid under conditions where t
and
τ
-t
are met. If either t
or
τ
-t
are not met, the part will operate but the Pipe line De-
lay is increased by 2 additional CLOCK cycles for 2:1 Mode and is increased by 4 additional CLOCK cycles for 4:1 Mode, after calibration is performed.
7
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10%
and 90% points of full-scale transition. T ransition time measured from the 50% point of full-scale transition to the output remaining within 2% of the final output
value. (T ransition time does not include clock and data feedthrough.)
8
t
23
and t
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V.
9
t
is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapo-
lated back to remove the effects of charging the 100 pF capacitor. T his means that the time, t
25
, quoted in the T iming Characteristics is the true value for the device
and as such is independent of external databus loading capacitances.
Specifications subject to change without notice.
I
SINK
+2.1V
TO
OUTPUT
PIN
I
SOURCE
100pF
Figure 1. Load Circuit for Databus Access and Relinquish Times
t
3
t
2
CLOCK
LOADOUT
(1:1 MULTIPLEXING)
LOADOUT
(2:1 MULTIPLEXING)
LOADOUT
(4:1 MULTIPLEXING)
CLOCK
t
4
t
1
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK,
CLOCK
)
PIXEL INPUT
DATA*
LOADIN
t
8
t
9
VALID
DATA
VALID
DATA
VALID
DATA
t
5
t
6
*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC
t
7
Figure 3. LOADIN vs. Pixel Input Data
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