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ADV7150
–22–
REV. A
COMMAND RE GIST E R 2 (CR2)
(Address Reg (A7–A0) = 06H)
T his register contains a number of control bits as shown in the
diagram. CR2 is a 10-bit wide register. However, for program-
ming purposes, it may be considered as an 8-bit-wide register
(CR28 and CR29 are both reserved).
T he diagram shows the various operations under the control of
CR2. T his register can be read from as well written to. In read
mode, CR28 and CR29 are both returned as zeros.
COMMAND RE GIST E R 2-BIT DE SCRIPT ION
R7 T rigger Polarity Control (CR 20)
T his bit is used when the device is in test/diagnostic mode. It
determines whether the pixel data is latched into the test regis-
ters in the rising or falling edge of R7. (See T est Diagnostics
section.)
I
PLL
T rigger Control (CR21)
T his bit specifies whether the I
PLL
output is triggered from
BLANK
or
SYNC
.
SYNC
Recognition Control (CR22)
T his bit specifies whether the video
SYNC
input is to be
encoded onto the IOG analog output or ignored.
Pedestal E nable Control (CR23)
T his bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes-
tal is to be generated on the video outputs.
T rue-Color/Pseudo-Color Mode Control (CR27–CR24)
T hese 4 bits specify the various color modes. T hese include a
24-bit true-color mode, two 15-bit true-color modes and three
8-bit pseudo color modes.
CR20
RESERVED*
CR26
CR25
CR24
CR27
0
1
CR21
I
PLL
TRIGGER CONTROL
SYNC
BLANK
R7 TRIGGER
POLARITY CONTROL
0
1
CR20
CR29
CR28
CR22
0
1
IGNORE
DECODE
SYNC RECOGNITION
CONTROL
*THESE BITS ARE READ-
ONLY RESERVED BITS.
A READ CYCLE WILL
RETURN ZEROS "00."
CR21
CR23
CR22
TRUE COLOR/PSEUDO-COLOR MODE CONTROL
MODE
0
1
1
1
1
0
1
0
0
0
0
1
1
0
0
0
1
1
0
1
CR27
CR26
CR24
CR25
0
0
0
0
8-BIT PSEUDO COLOR ON R7–R0
8-BIT PSEUDO COLOR ON G7–G0
8-BIT PSEUDO COLOR ON B7–B0
15-BIT TRUE COLOR ON
R7–R3, G7–G3, B7–B3
15-BIT TRUE COLOR ON
R7–R0, G6–G0
24-BIT TRUE COLOR
R7–R0, G7–G0, B7–B0
PEDESTAL ENABLE
CONTROL
CR23
0
1
0 IRE
7.5 IRE
Command Register 2 (CR2) (CR29–CR20)