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ADV7150
–19–
REV. A
T able III. Interface T ruth T able (10-Bit Databus Mode)
R/
W
C1
C0
Databus (D9–D0)
Operation
Result
0
0
0
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Write to Mode Register
Write to Address Register
Write to Control Registers
(
Particular Control Register Determined by Address Register
)
DB7–DB0
MR17–MR10
DB7–DB0
A7–A0
DB7–DB0
Control Register
0
0
0
0
0
0
1
1
1
DB9–DB0
DB9–DB0
DB9–DB0
Write to RED Register
Write to GREEN Register
Write to BLUE Register
Write RGB Data to RAM Location Pointed to by Address Register (A7–A0)
Address Register = Address Register + 1
DB9–DB0
R9–R0
DB9–DB0
G9–G0
DB9–DB0
B9–B0
1
1
1
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Read Mode Register
Read Address Register
Read Control Registers
(Particular Control Register Determined by Address Register)
MR17–MR10
DB7–DB0
A7–A0
DB7–DB0
Register Data
DB7–DB0
1
1
1
0
0
0
1
1
1
DB9–DB0
DB9–DB0
DB9–DB0
Read RED RAM Location
Read GREEN RAM Location
Read BLUE RAM Location
(RAM Location Pointed to by Address Register(A7–A0))
Address Register = Address Register + 1
R9–R0
DB9–DB0
G9–G0
DB9–DB0
B9–B0
DB9–DB0
DB = Data Bit.
T able IV. Interface T ruth T able (8-Bit Databus Mode)*
R/
W
C1
C0
Databus (D7–D0)
Operation
Result
0
0
0
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Write to Mode Register
Write to Address Register
Write to Control Registers
(
Particular Control Register Determined by Address Register
(
A7–A0
))
DB7–DB0
MR17–MR10
DB7–DB0
A7–A0
DB7–DB0
Control Registers
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
Write to RED Register
Write to RED Register
Write to GREEN Register
Write to GREEN Register
Write to BLUE Register
Write to BLUE Register
Write RGB Data to RAM Location Pointed to by Address Register (A7-A0)
Address Register = Address Register + 1
DB9–DB2
R9–R2
DB1–DB0
R1–R0
DB9–DB2
G9–G2
DB1–DB0
G1–G0
DB9–DB2
B9–B2
DB1–DB0
B1–B0
1
1
1
1
0
1
1
0
0
DB7–DB0
DB7–DB0
DB7–DB0
Read Mode Register
Read Address Register
Read Control Registers
(Particular Control Register Determined by Address Register)
MR17–MR10
DB7–DB0
A7–A0
DB7–DB0
Register Data
DB7–DB0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
DB9–DB2
DB1–DB0
Read RED RAM Location
Read RED RAM Location
Read GREEN RAM Location
Read GREEN RAM Location
Read BLUE RAM Location
Read BLUE RAM Location
(RAM Location Pointed to by Address Register (A7–A0))
Address Register = Address Register + 1
R9–R2
DB9–DB2
R1–R0
DB1–DB0
G9–G2
DB9–DB2
G1–G0
DB1–DB0
B9–B2
DB9–DB2
B1–B0
DB1–DB0
*Writing or reading 10-bit data (DB9–DB0) over an 8-bit databus (D7–D0) requires two write or two read cycles.
:DB9–DB2 is mapped to D7–D0 on the first cycle.
:DB1–DB0 is mapped to D1–D0 on the second cycle.
DB = Data Bit.