參數(shù)資料
型號: ADV7123
廠商: Analog Devices, Inc.
英文描述: CMOS, 240 MHz Triple 10-Bit High Speed Video DAC(240MHz三通道10位高速視頻D/A轉(zhuǎn)換器)
中文描述: 的CMOS,240 MHz的三路10位高速視頻DAC(240MHz的三通道10位高速視頻的D / A轉(zhuǎn)換器)
文件頁數(shù): 6/16頁
文件大?。?/td> 318K
代理商: ADV7123
ADV7123
5 V TIMING–SPECIFICATIONS
1
–6–
REV. A
Parameter
Min
Typ
Max
Units
Condition
ANALOG OUTPUTS
Analog Output Delay, t
6
Analog Output Rise/Fall Time, t
74
Analog Output Transition Time, t
85
Analog Output Skew, t
96
CLOCK CONTROL
f
CLK7
f
CLK7
f
CLK7
Data and Control Setup, t
1
Data and Control Hold, t
2
Clock Pulsewidth High, t
4
Clock Pulsewidth Low t
5
Clock Pulsewidth High t
4
Clock Pulsewidth Low t
5
Clock Pulsewidth High t
4
Clock Pulsewidth Low t
5
Pipeline Delay, t
PD6
PSAVE
Up Time, t
106
5.5
1.0
15
1
ns
ns
ns
ns
2
0.5
0.5
0.5
1.5
2.5
1.875
1.875
2.85
2.85
8.0
8.0
1.0
50
140
240
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
1.1
1.25
f
MAX
= 240 MHz
f
MAX
= 240 MHz
f
MAX
= 140 MHz
f
MAX
= 140 MHz
f
MAX
= 50 MHz
f
MAX
= 50 MHz
1.0
2
1.0
10
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) 0 for both 5 V and 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
MIN
to T
MAX
: –40
°
C to +85
°
C at 50 MHz and 140 MHz, 0
°
C to +70
°
C at 240 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
(V
AA
= +5 V
6
5%
2
, V
REF
= 1.235 V, R
SET
= 560
V
, C
L
= 10 pF. All specifications T
MIN
to T
MAX3
unless otherwise noted, T
J
MAX
= 110
8
C)
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