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參數(shù)資料
| 型號： | ADV7123 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, 240 MHz Triple 10-Bit High Speed Video DAC(240MHz三通道10位高速視頻D/A轉(zhuǎn)換器) |
| 中文描述： | 的CMOS，240 MHz的三路10位高速視頻DAC（240MHz的三通道10位高速視頻的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 318K |
| 代理商： | ADV7123 |
ADV7123
–14–
REV. A
Therefore, if we have a graphics system with a 1024
×
1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace
factor of 0.8, then:
Dot Rate =
1024
×
1024
×
60/0.8
=
78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7123
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7123 be driven by a TTL buffer (e.g., 74F244).
Video Synchronization and Control
The ADV7123 has a single composite sync (
SYNC
) input con-
trol. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite
SYNC
.
In a graphics system that does not automatically generate a
composite
SYNC
signal, the inclusion of some additional logic
circuitry will enable the generation of a composite
SYNC
signal.
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7123, the
SYNC
input should be tied
to logic low.
Reference Input
The ADV7123 contains an onboard voltage reference. The V
REF
pin is normally terminated to V
AA
through a 0.1
μ
F capacitor.
Alternatively, the part could, if required, be overdriven by an
external 1.23 V reference (AD1580).
A resistance R
SET
connected between the R
SET
pin and GND
determines the amplitude of the output video level according to
Equations 1, 2 for the ADV7123:
IOG
* (
mA
) = 12,081
×
V
REF
(V)/
R
SET
(
) (1)
IOR, IOB (mA) =
8,627
×
V
REF
(V)/R
SET
(
)
*
Applies to the ADV7123 only when
SYNC
is being used. If
SYNC
is not being
encoded onto the green channel, Equation 1 will be similar to Equation 2.
Using a variable value of R
SET
, as shown in Figure 22, allows for
accurate adjustment of the analog output video levels. Use of a
fixed 560
R
SET
resistor yields the analog output levels as quoted
in the specification page. These values typically correspond to
the RS-343A video waveform values as shown in Figure 21.
D/A Converters
The ADV7123 contains three matched 10-bit D/A converters.
The DACs are designed using an advanced, high speed, seg-
mented architecture. The bit currents corresponding to each
digital input are routed to either the analog output (bit = “1”) or
GND (bit = “0”) by a sophisticated decoding scheme. As all this
circuitry is on one monolithic device, matching between the
three DACs is optimized. As well as matching, the use of identi-
cal current sources in a monolithic design guarantees monoto-
nicity and low glitch. The onboard operational amplifier stabilizes
the full-scale output current against temperature and power
supply variations.
Analog Outputs
The ADV7123 has three analog outputs, corresponding to the
red, green and blue video signals.
(2)
The red, green and blue analog outputs of the ADV7123 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5
load, such
as a doubly terminated 75
coaxial cable. Figure 22a shows the
required configuration for each of the three RGB outputs con-
nected into a doubly terminated 75
load. This arrangement
will develop RS-343A video output voltage levels across a 75
monitor.
A suggested method of driving RS-170 video levels into a 75
monitor is shown in Figure 22b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
Z
S
, on each of the three DACs is increased from 75
to 150
.
IOR, IOG, IOB
Z
O
= 75
V
(CABLE)
Z
S
= 75
V
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Z
= 75
V
(MONITOR)
DACs
Figure 22a. Analog Output Termination for RS-343A
IOR, IOG, IOB
Z
O
= 75
V
(CABLE)
Z
S
= 150
V
(SOURCE
TERMINATION)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Z
= 75
V
(MONITOR)
DACs
Figure 22b. Analog Output Termination for RS-170
More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an Application Note entitled “Video Formats &
Required Load Terminations” available from Analog Devices,
publication no. E1228–15–1/89.
Figure 21 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75
load of Figure
22a. As well as the gray scale levels, Black Level to White Level,
the diagram also shows the contributions of
SYNC
and
BLANK
for the ADV7123. These control inputs add appropriately
weighted currents to the analog outputs, producing the spe-
cific output level requirements for video applications. Table I
details how the
SYNC
and
BLANK
inputs modify the output
levels.
Gray Scale Operation
The ADV7123 can be used for stand-alone, gray scale (mono-
chrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels,
RED, GREEN or BLUE can be used to input the digital video
data. The two unused video data channels should be tied to
logical zero. The unused analog outputs should be terminated
with the same load as that for the used channel. In other words,
if the red channel is used and IOR is terminated with a doubly
terminated 75
load (37.5
), IOB and IOG should be termi-
nated with 37.5
resistors. See Figure 23.
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