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參數(shù)資料
| 型號(hào)： | ADV7123 |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 英文描述： | CMOS, 240 MHz Triple 10-Bit High Speed Video DAC(240MHz三通道10位高速視頻D/A轉(zhuǎn)換器) |
| 中文描述： | 的CMOS，240 MHz的三路10位高速視頻DAC（240MHz的三通道10位高速視頻的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 318K |
| 代理商： | ADV7123 |
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–5–
REV. A
ADV7123
3.3 V DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
2
Single-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
f
CLK
= 50 MHz; f
OUT
= 2.51 MHz
f
CLK
= 50 MHz; f
OUT
= 5.04 MHz
f
CLK
= 50 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 2.51 MHz
f
CLK
= 100 MHz; f
OUT
= 5.04 MHz
f
CLK
= 100 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 40.4 MHz
f
CLK
= 140 MHz; f
OUT
= 2.51 MHz
f
CLK
= 140 MHz; f
OUT
= 5.04 MHz
f
CLK
= 140 MHz; f
OUT
= 20.2 MHz
f
CLK
= 140 MHz; f
OUT
= 40.4 MHz
Double-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
f
CLK
= 50 MHz; f
OUT
= 2.51 MHz
f
CLK
= 50 MHz; f
OUT
= 5.04 MHz
f
CLK
= 50 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 2.51 MHz
f
CLK
= 100 MHz; f
OUT
= 5.04 MHz
f
CLK
= 100 MHz; f
OUT
= 20.2 MHz
f
CLK
= 100 MHz; f
OUT
= 40.4 MHz
f
CLK
= 140 MHz; f
OUT
= 2.51 MHz
f
CLK
= 140 MHz; f
OUT
= 5.04 MHz
f
CLK
= 140 MHz; f
OUT
= 20.2 MHz
f
CLK
= 140 MHz; f
OUT
= 40.4 MHz
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz; 1 MHz Span
f
CLK
= 50 MHz; f
OUT
= 5.04 MHz; 2 MHz Span
f
CLK
= 140 MHz; f
OUT
= 5.04 MHz; 4 MHz Span
Double-ended Output
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz; 1 MHz Span
f
CLK
= 50 MHz; f
OUT
= 5.00 MHz; 2 MHz Span
f
CLK
= 140 MHz; f
OUT
= 5.00 MHz; 4 MHz Span
Total Harmonic Distortion
f
CLK
= 50 MHz; f
OUT
= 1.00 MHz
T
A
= +25
°
C
T
MIN
to T
MAX
f
CLK
= 50 MHz; f
OUT
= 2.00 MHz
f
CLK
= 100 MHz; f
OUT
= 2.00 MHz
f
CLK
= 140 MHz; f
OUT
= 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC Crosstalk
3
Data Feedthrough
4, 5
Clock Feedthrough
4, 5
67
67
63
55
62
60
54
48
57
58
52
41
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70
70
65
54
67
63
58
52
62
61
55
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
77
73
64
dBc
dBc
dBc
74
73
60
dBc
dBc
dBc
66
65
64
64
55
dBc
dBc
dBc
dBc
dBc
10
23
22
33
pVs
dB
dB
dB
NOTES
1
These max/min specifications are guaranteed by characterization over 3.0 V to 3.6 V range.
2
Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V
REF
.
3
DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.
4
Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5
TTL input values are 0 V to 3 V, with input rise/fall times
≤
3 ns, measured the 10% and 90% points. Timing reference points is 50% for inputs and outputs.
Specifications subject to change without notice.
(V
AA
= +3.0 V–3.6 V
1
, V
REF
= 1.235 V, R
SET
= 680
V
, C
L
= 10 pF. All specifications are
T
A
= +25
8
C unless otherwise noted, T
J
MAX
= 110
8
C)
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