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參數(shù)資料
| 型號： | ADV3225ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SW 16X8 72LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 16:8 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±5V |
| 電流 - 電源： | 58mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP-VQ（10x10） |
| 包裝： | 托盤 |
ADV3224/ADV3225
Rev. A | Page 22 of 24
APPLICATIONS INFORMATION
The ADV3224/ADV3225 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 40 bits can be provided, which updates the entire
matrix each time the 40-bit word is shifted into the device. The
second option allows for changing the programming of a single
output via a parallel interface. The serial option requires fewer
signals but more time (clock cycles) for changing the program-
ming, whereas the parallel programming technique requires
more signals but can change a single output at a time and requires
fewer clock cycles to complete the programming.
SERIAL PROGRAMMING
The serial programming mode uses the CE, CLK, DATAIN,
UPDATE, and SER/PAR pins. The first step is to assert a low
on SER/PAR to enable the serial programming mode. CE must
be low to allow data to be clocked into the device. The
The
CE signal
can be used to address an individual device when devices are
connected in parallel.
UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when
The data at DATAIN is clocked in at every falling edge of CLK,
and a total of 40 bits must be shifted in to complete the program-
ming. For each of the eight outputs, there are four bits (D0 to
D3) that determine the source of its input. The MSB is shifted
in first. A fifth bit (D4) precedes the four input select bits and
determines the enabled state of the output. If D4 is low (output
disabled), the four associated bits (D0 to D3) do not matter
because no input switches to that output.
UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix, which causes
the matrix to try to update to every intermediate state as defined by
the shifting data.
The most significant output address data is shifted in first, and
the remaining addresses follow in sequence until the least signifi-
cant output address data is shifted in. At this point, UPDATE
can be taken low, which programs the device according to the
data that was just shifted in. The update registers are asynchronous,
and when UPDATE is low (and CE
If more than one ADV3224/ADV3225 device is to be serially
programmed in a system, the DATAOUT signal from one
device can be connected to the DATAIN of the next device to
form a serial chain. Connect all of the CLK,
is low), they are transparent.
CE, UPDATE, and
SER
PARALLEL PROGRAMMING
/PAR pins in parallel and operate them as described previously
in this section. The serial data is input to the DATAIN pin of
the first device of the chain, and it ripples through to the last.
Therefore, the data for the last device in the chain should come
at the beginning of the programming sequence. The length of
the programming sequence (40 bits) is multiplied by the number
of devices in the chain.
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
Parallel programming allows the modification of a single output
at a time. Because this takes only one CLK/UPDATE
An important consideration in using parallel programming is
that the
cycle, signifi-
cant time savings can be realized by using parallel programming.
RESET signal does not reset all registers in the ADV3224/
ADV3225. When taken low, the
After initial power-up, the internal registers in the device
generally contain random data, even though the
RESET signal sets each output
to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.
RESET
Similarly, if both
signal
was asserted. If parallel programming is used to program one
output, that output is properly programmed, but the rest of the
device has a random program state depending on the internal
register content at power-up. Therefore, when using parallel
programming, it is essential that all outputs be programmed to
a desired state after power-up to ensure that the programming
matrix is always in a known state. From this point, parallel pro-
gramming can be used to modify either a single output or multiple
outputs at one time.
CE and UPDATE are taken low after initial
power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent programming
the crosspoint into an unknown state, do not apply low logic
levels to both CE and
To change the programming of an output via parallel program-
ming, take the
UPDATE after power is initially applied.
To eliminate the possibility of programming the matrix to an
unknown state, after initial power-up, program the full shift
register one time to a desired state using either serial or parallel
programming.
SER/PAR and UPDATE pins high, and take the
CE
The first four data bits (D0 to D3) contain the information that
identifies the input that is programmed to the addressed output.
The fifth data bit (D4) determines the enabled state of the out-
put. If D4 is low (output disabled), the data on D0 to D3 does
not matter.
pin low. The CLK signal should be in the high state. Place
the 3-bit address of the output to be programmed on A0 to A2.
After the address and data signals are established, they can be
latched into the shift register by pulling the CLK signal low;
however, the matrix is not programmed until the UPDATE
signal is taken low. In this way, it is possible to latch in new data
for several or all of the outputs first via successive negative transi-
tions of CLK while UPDATE is held high and then have all the
new data take effect when UPDATE goes low. Use this technique
when programming the device for the first time after power-up
when using parallel programming. In parallel mode, the CLK
pin is level sensitive, whereas in serial mode, it is edge triggered.
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