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| 型號(hào)： | ADV3225ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SW 16X8 72LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開(kāi)關(guān) |
| 電路： | 1 x 16:8 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±5V |
| 電流 - 電源： | 58mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 72-LFCSP-VQ（10x10） |
| 包裝： | 托盤(pán) |
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ADV3224/ADV3225
Rev. A | Page 21 of 24
THEORY OF OPERATION
The ADV3224 (G = +1) and ADV3225 (G = +2) are crosspoint
arrays with eight outputs, each of which can be connected to
any one of 16 inputs. Organized by output row, 16 switchable
input transconductance stages are connected to each output
buffer to form 16-to-1 multiplexers. There are eight of these
multiplexers, each with its inputs wired in parallel, for a total array
of 128 transconductance stages forming a multicast-capable
crosspoint switch. Each input is buffered and is not loaded by
the outputs, simplifying the construction of larger arrays using the
ADV3224 or ADV3225 as a building block.
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier. A mask programmable feedback
network sets the closed-loop signal gain. For the ADV3224, this
gain is +1, and for the ADV3225, this gain is +2.
The output stage of the ADV3224 or ADV3225 is designed for
low differential gain and phase error when driving composite
video signals. It also provides slew current for a fast pulse response
when driving component video signals. Unlike many multiplexer
designs, these requirements are balanced such that large signal
bandwidth is very similar to small signal bandwidth. The design
load is 150 , but provisions are made to drive loads as low as
100 when on-chip power dissipation limits are not exceeded.
The outputs of the ADV3224/ADV3225 can be disabled to mini-
mize on-chip power dissipation. When disabled, there is no
feedback network loading the output. This high disabled output
impedance allows multiple ICs to be bussed together without
additional buffering. Take care to reduce output capacitance,
which results in more overshoot and frequency domain
peaking.
A series of internal amplifiers drives internal nodes such that a
wideband high impedance is presented at the disabled output,
even while the output bus is under large signal swings. To keep
these internal amplifiers in their linear range of operation when
the outputs are disabled and driven externally, do not allow the
voltage applied to them to exceed the valid output swing range
for the ADV3224/ADV3225. If the disabled outputs are left
floating, they may exhibit high enable glitches. If necessary,
the disabled output can be kept from drifting out of range by
applying an output load resistor to ground.
The connection of the ADV3224/ADV3225 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the second
rank of latches, simultaneously updating all outputs. In serial
mode, a serial output pin allows devices to be daisy-chained
together for single pin programming of multiple ICs. A power-
on reset pin is available to avoid bus conflicts by disabling all
outputs. This power-on reset clears the second rank of latches
but does not clear the first rank of latches. In serial mode, pre-
programming individual inputs is not possible and the entire
shift register must be flushed.
To easily interface to ground referenced video signals, the
ADV3224/ADV3225 operate on split ±5 V supplies. The logic
inputs and output run on a single 5 V supply, and the logic
inputs switch at approximately 1.6 V for compatibility with a
variety of logic families. The serial output buffer is a rail-to-
rail output stage with 5 mA of drive capability.
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| ADV3226 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:750 MHz, 16 × 16 Analog Crosspoint Switch |
| ADV3226ACPZ | 功能描述:IC CROSSPOINT SW 16X16 100LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
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