參數(shù)資料
型號(hào)： ADUC832BSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 83/92頁
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
ADuC832
Data Sheet
Rev. B | Page 84 of 92
POWER CONSUMPTION
The currents consumed by the various sections of the ADuC832
are shown in Table 50. The core values given represent the
current drawn by DVDD, and the rest (ADC, DAC, voltage
reference) are pulled by the AVDD pin and can be disabled in
software when not in use. The other on-chip peripherals (for
example, watchdog timer and power supply monitor) consume
negligible current and are therefore included with the core
operating current. The user must add any currents sourced by
the parallel and serial I/O pins and by the DAC to determine
the total current needed at the ADuC832 supply pins. Also,
current drawn from the DVDD supply increases by approx-
imately 10 mA during Flash/EE erase and program cycles.
Table 50. Typical IDD of Core and Peripherals
Core/Peripherals
VDD = 5 V
VDD = 3 V
Core, Normal Mode
(1.6 nA × MCLK) +
6 mA
(0.8 nA × MCLK) +
3 mA
Core, Idle Mode
(0.75 nA × MCLK) +
5 mA
(0.25 nA × MCLK) +
3 mA
ADC
1.3 mA
1.0 mA
DAC (Each)
250 μA
200 μA
Voltage Reference
200 μA
150 μA
Because the operating DVDD current is primarily a function of
clock speed, the expressions for core supply current in Table 50
are given as functions of MCLK, the core clock frequency. Use a
value for MCLK in hertz to determine the current consumed by
the core at that oscillator frequency. Because the ADC and
DACs can be enabled or disabled in software, add only the
currents from the peripherals that are expected to be used. Do
not forget to include current sourced by I/O pins, serial port
pins, and DAC outputs, plus the additional current drawn
during Flash/EE erase and program cycles. A software switch
allows the chip to be switched from normal mode into idle
mode, and into full power-down mode. The following sections
provide brief descriptions of power-down and idle modes.
POWER SAVING MODES
In idle mode, the oscillator continues to run but the core clock
generated from the PLL is halted. The on-chip peripherals
continue to receive the clock, and remain functional. The CPU
status is preserved with the stack pointer and program counter,
and all other internal registers maintain their data during idle
mode. Port pins and DAC output pins retain their states in this
mode. The chip recovers from idle mode upon receiving any
enabled interrupt, or upon receiving a hardware reset.
In full power-down mode, both the PLL and the clock to the
core are stopped. The on-chip oscillator can be halted or can
continue to oscillate depending on the state of the oscillator
power-down bit (OSC_PD) in the PLLCON SFR. The TIC,
being driven directly from the oscillator, can also be enabled
during power-down. All other on-chip peripherals, however, are
shut down. Port pins retain their logic levels in this mode, but
the DAC output goes to a high impedance state (three-state).
During full power-down mode, the ADuC832 consumes a total
of approximately 20 μA. There are five ways of terminating
power-down mode.
Asserting the RESET Pin
Asserting the RESET pin returns the part to normal mode. All
registers are set to their default state and program execution
starts at the reset vector when the RESET pin is deasserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR returns the core
to the instruction following the one that enabled power-down.
I2C or SPI Interrupt
Power-down mode is terminated and the CPU services the
I2C/SPI interrupt. The RETI at the end of the ISR returns the
core to the instruction following the one that enabled power-
down. It should be noted that the I2C/SPI power-down
interrupt enable bit (SERIPD) in the PCON SFR must first be
set to allow this mode of operation.
INT0 Interrupt
Power-down mode is terminated and the CPU services the
INT0 interrupt. The RETI at the end of the ISR returns the core
to the instruction following the one that enabled power-down.
The INT0 pin must not be driven low during or within two
machine cycles of the instruction that initiates power-down
mode. It should be noted that the INT0 power-down interrupt
enable bit (INT0PD) in the PCON SFR must first be set to allow
this mode of operation.
POWER-ON RESET
An internal power-on reset (POR) is implemented on the
ADuC832. For DVDD below 2.45 V, the internal POR holds
the ADuC832 in reset. As DVDD rises above 2.45 V, an internal
timer times out for approximately 128 ms before the part is
released from reset. The user must ensure that the power supply
has reached a stable 2.7 V minimum level by this time. Likewise
upon power-down, the internal POR holds the ADuC832 in reset
until the power supply drops below 1 V. Figure 92 illustrates the
operation of the internal POR in detail.
128ms TYP
1.0V TYP
128ms TYP
2.45V TYP
1.0V TYP
INTERNAL
CORE RESET
DVDD
0
29
87-
0
80
Figure 92. Internal POR Operation
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