參數(shù)資料
型號(hào)： ADUC832BSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/92頁(yè)
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 800
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 帶卷 (TR)
Data Sheet
ADuC832
Rev. B | Page 33 of 92
SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only.
It provides an interface between the CPU and all on-chip peripher-
als. A block diagram showing the programming model of the
ADuC832 via the SFR area is shown in Figure 35.
All registers, except the program counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
62-kB
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
8051-
COMPATIBLE
CORE
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
2
12-BIT DACs
SERIAL I/O
WDT
PSM
TIC
PWM
8-CHANNEL
12-BIT ADC
4-kB
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
2304 BYTES
RAM
02987-
024
Figure 35. Programming Model
ACCUMULATOR SFR (ACC)
ACC is the accumulator register and is used for math operations
including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.
B SFR (B)
The B register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated
as a general-purpose scratch pad register.
STACK POINTER (SP AND SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the top of the stack. The SP register
is incremented before data is stored during push and call
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at Location 08H.
As mentioned previously, the ADuC832 offers an extended
11-bit stack pointer. The three extra bits to make up the 11-bit
stack pointer are the three LSBs of the SPH byte located at B7H.
DATA POINTER (DPTR)
The data pointer is made up of three 8-bit registers, named DPP
(page byte), DPH (high byte), and DPL (low byte). These are
used to provide memory addresses for internal and external
code access and external data access. It can be manipulated as a
16-bit register (DPTR = DPH, DPL), although INC DPTR
instructions automatically carry over to DPP, or as three
independent 8-bit registers (DPP, DPH, and DPL).
The ADuC832 supports dual data pointers. Refer to the Dual
PROGRAM STATUS WORD (PSW)
SFR Address:
D0H
Power-On Default Value:
00H
Bit Addressable:
Yes
The PSW SFR contains several bits reflecting the current status
of the CPU, as detailed in Table 14.
Table 14. PSW SFR Bit Designations
Bit
Name
Description
[7]
CY
Carry flag
[6]
AC
Auxiliary carry flag
[5]
F0
General-purpose flag
[4:3]
RS[1:0]
Register bank select bits
RS1
RS0
Selected Bank
0
1
0
2
1
3
[2]
OV
Overflow flag
[1]
F1
General-purpose flag
[0]
P
Parity bit
POWER CONTROL SFR (PCON)
SFR Address:
87H
Power-On Default Value:
00H
Bit Addressable:
No
The PCON SFR contains bits for power-saving options and
general-purpose status flags, as shown in Table 15.
Table 15. PCON SFR Bit Designations
Bit
Name
Description
[7]
SMOD
Double UART baud rate
[6]
SERIPD
I2C/SPI power-down interrupt enable
[5]
INT0PD
INT0 power-down interrupt enable
[4]
ALEOFF
Disable ALE output
[3]
GF1
General-purpose flag bit
[2]
GF0
General-purpose flag bit
[1]
PD
Power-down mode enable
[0]
IDL
Idle mode enable
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