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參數(shù)資料
| 型號： | ADUC832BSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 52MQFP |
| 標準包裝： | 800 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC832
Rev. B | Page 49 of 92
EXAMPLE: PROGRAMMING THE FLASH/EE DATA
MEMORY
To program F3H into the second byte on Page 03H of the
Flash/EE data memory space while preserving the other three
bytes already in this page, a typical program of the Flash/EE
data array includes the following steps:
1. Setting EADRH/L with the page address
2. Writing the data to be programmed to EDATA1 to
EDATA4
3. Writing the ECON SFR with the appropriate command
Step 1: Set Up the Page Address
The two address registers, EADRH and EADRL, hold the high
byte address and the low byte address of the page to be
addressed.
The assembly language to set up the address may appear as:
MOV EADRH,#0
; Set Page Address Pointer
MOV EADRL,#03H
Step 2: Set Up the EDATA Registers
Next, write the four values to be written into the page into the
four SFRs, EDATA1 to EDATA4. Unfortunately, three of these
are unknown. Thus, the current page must be read and the
second byte overwritten.
MOV ECON,#1
; Read Page into EDATA1 to
EDATA4
MOV EDATA2,#0F3H
; Overwrite Byte 2
Step 3: Program Page
A byte in the Flash/EE array can only be programmed if it has
previously been erased; that is, a byte can only be programmed
if it already holds the value FFH. Because of the Flash/EE architec-
ture, this erase must happen at a page level; therefore, a minimum
of four bytes (one page) is erased when an erase command is
initiated. Once the page is erased, the four bytes can be pro-
grammed in-page and then a verification of the data performed.
MOV ECON,#5
; ERASE Page
MOV ECON,#2
; WRITE Page
MOV ECON,#4
; VERIFY Page
MOV A,ECON
; Check if ECON = 0 (OK!)
JNZ ERROR
Although the 4 kB of Flash/EE data memory are shipped from
the factory pre-erased, that is, byte locations set to FFH, it is
nonetheless good programming practice to include an erase-all
routine as part of any configuration/setup code running on the
ADuC832. An erase all command consists of writing 06H to the
ECON SFR, which initiates an erase of the 4 kB Flash/EE array.
This command coded in 8051 assembly appears as:
MOV ECON,#06H
; Erase all Command
; 2 ms Duration
FLASH/EE MEMORY TIMING
Typical program and erase times for the ADuC832 are as
detailed in Table 22 and Table 23.
Table 22. Normal Mode (Operating on Flash/EE Data
Memory)
Instruction
Time
READPAGE (4 bytes)
5 machine cycles
WRITEPAGE (4 bytes)
380 μs
VERIFYPAGE (4 bytes)
5 machine cycles
ERASEPAGE (4 bytes)
2 ms
ERASEALL (4 kB)
2 ms
READBYTE (1 byte)
3 machine cycle
WRITEBYTE (1 byte)
200 μs
Table 23. ULOAD Mode (Operating on Flash/EE Program
Memory)
Instruction
Time
WRITEPAGE (256 bytes)
15 ms
ERASEPAGE (64 bytes)
2 ms
ERASEALL (56 kB)
2 ms
WRITEBYTE (1 byte)
200 μs
Note that a given mode of operation is initiated as soon as
the command word is written to the ECON SFR. The core
microcontroller operation on the ADuC832 is idled until
the requested program/read or erase mode is completed.
In practice, this means that even though the Flash/EE memory
mode of operation is typically initiated with a two-machine
cycle MOV instruction (to write to the ECON SFR), the next
instruction is not executed until the Flash/EE operation is com-
plete. This means that the core does not respond to interrupt
requests until the Flash/EE operation is complete, although the
core peripheral functions such as counter/timers continue to
count and keep time as configured throughout this period.
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