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參數(shù)資料
| 型號(hào)： | ADUC814BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 41 of 72
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
or interrupt within a reasonable amount of time if the ADuC814
enters an erroneous state, possibly due to a programming error,
electrical noise, or RFI. The watchdog function can be disabled
by clearing the WDE (watchdog enable) bit in the watchdog
control (WDCON) SFR. When enabled, the watchdog circuit
generates a system reset or interrupt (WDS) if the user program
fails to set the watchdog (WDE) bit within a predetermined
amount of time (see PRE3–0 bits in WDCON). The watchdog
timer itself is a 16-bit counter that is clocked at 32.768 kHz. The
watchdog timeout interval can be adjusted via the PRE3–0 bits
in WDCON. Full control and status of the watchdog timer
function can be controlled via the watchdog timer control SFR
(WDCON). The WDCON SFR can be written only by the user
software if the double write sequence (WDWR) described in
Table 15 is initiated on every write access to the WDCON SFR.
WDCON
Watchdog Timer Control Register
SFR Address
C0H
Power-On Default
10H
Bit Addressable
Yes
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
Table 15. WDCON SFR Bit Designation
Bit No.
Name
Description
7
PRE3
6
PRE2
5
PRE1
Watchdog Timer Prescale Bits.
The watchdog timeout period is given by the equation
tWD = (2PRE × (29/fPLL))
where fPLL = 32.768 kHz and PRE is defined as follows:
PRE3
PRE2
PRE1
PRE0
Timeout Period (ms)
Action
0
15.6
Reset or Interrupt
0
1
31.2
Reset or Interrupt
0
1
0
62.5
Reset or Interrupt
0
1
125
Reset or Interrupt
0
1
0
250
Reset or Interrupt
0
1
0
1
500
Reset or Interrupt
0
1
0
1000
Reset or Interrupt
0
1
2000
Reset or Interrupt
1
0
0.0
Immediate Reset
4
PRE0
PRE3–0 > 1001
Reserved
3
WDIR
Watchdog Interrupt Request.
If this bit is set by the user, the watchdog generates an interrupt response instead of a system reset when the
watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed,
high-priority interrupt.
If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used
to set the timeout period in which an interrupt is generated. (See Table 33, Note 1, in the Interrupt System section.)
2
WDS
Watchdog Status Bit.
Set by the watchdog controller to indicate that a watchdog timeout has occurred.
Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset.
1
WDE
Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user within the watchdog
timeout period, the watchdog generates a reset or interrupt, depending on WDIR.
Cleared under the following conditions: User writes 0, Watchdog Reset (WDIR = 0); Hardware Reset; PSM Interrupt.
0
WDWR
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and followed
immediately by a write instruction to the WDCON SFR. For example:
CLR EA
; disable interrupts while writing to WDT
SETB WDWR
; allow write to WDCON
MOV WDCON, #72H
; enable WDT for 2.0s timeout
SET B EA
; enable interrupts again (if rqd)
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