參數(shù)資料
型號： ADUC7121BBCZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 40/96頁
文件大小： 0K
描述： PRECISION ANALOG MCU I.C
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 9x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 標準包裝
其它名稱： ADUC7121BBCZ-RLDKR
Data Sheet
ADuC7121
Rev. B | Page 45 of 96
IDAC MMRs
Table 55. IDAC Control Registers (Read and Write Access)
Name
Address (Hex)
Default Value
IDAC0CON
0xFFFF0700
0x0010
IDAC1CON
0xFFFF070C
0x0010
IDAC2CON
0xFFFF0718
0x0010
IDAC3CON
0xFFFF0724
0x0010
IDAC4CON
0xFFFF0730
0x0010
TDSCON
0xFFFF073C
0x00
IDAC0PULLDOWN
0xFFFF0744
0x00
Table 56. IDACxCON MMR Bit Designations
Bit
Name
Value
Description
15:9
These bits are reserved.
8:7
SFHMODE
Bit shuffling is a method of
increasing the ac precision of an
IDAC. Do not use in applications
where dc performance is
important.
00
Shuffle one increment at a time.
01
Shuffle based on an internal
counter.
10
Shuffle based on the input data.
11
Reserved.
6
MSBSHFEN
0
MSB shuffle enable.
Set by the user to 1 to enable MSB
shuffling.
Set by the user to 0 to disable MSB
shuffling.
5
LSBSHFEN
0
LSB shuffle enable.
Set by the user to 1 to enable LSB
shuffling.
Set by the user to 0 to disable LSB
shuffling.
4
IDACPD
1
IDAC power-down bit.
Set by the user to 1 to power
down the IDAC. IDAC output is
high impedance.
Set by the user to 0 to power up
the IDAC.
3
IDACCLK
0
IDAC update rate.
Set by the user to update the IDAC
using Timer1.
Cleared by the user to update the
IDAC using HCLK (core clock).
2
IDACCLR
0
IDAC clear bit.
Set by the user to enable normal
IDAC operation.
Cleared by the user to reset data
register of the IDAC to 0.
1
Mode
0
Mode bit. This bit must always be
cleared.
0
Reserved
0
Set this bit to 0.
Table 57. TDSCON MMR Bit Designations
Bit
Value
Name
Description
7:3
Reserved
The user sets these bits to 0.
2
Reserved
The user must set this to 1.
1
0
DISINT
Disable thermal trigger interrupt.
Set by the user to 0 to generate an
interrupt if the temperature passes
the thermal shutdown point.
0
DISSD
Set by the user to 0 to disable the
output current DACs when the
temperature passes a trip point.
Table 58. IDAC0PULLDOWN MMR Bit Designations
Bit
Value
Name
Description
7:6
Reserved
These bits are set to 0 by the user.
5
0
Pulldown
IDAC0 pull-down.
Set to 1 by the user to pull down
the IDAC0 pin as well as power
down the IDAC0.
Set to 0 by the user to disable the
pull-down.
4
0
PLA_PD_EN
PLA output trigger enable.
Set to 1 by the user to enable the
PLA output to trigger the IDAC0
pull-down.
Set to 0 by the user to disable this
feature.
3:0
PLA Source
PLA output source for PLA output
trigger enable.
Can select the output of any
element, 0 to 15, by programming
these bits with the corresponding
binary value.
Table 59. IDAC Data Registers (Default Value = 0x00000000,
Read and Write Access)
Name
Address (Hex)
IDAC0DAT
0xFFFF0704
IDAC1DAT
0xFFFF0710
IDAC2DAT
0xFFFF071C
IDAC3DAT
0xFFFF0728
IDAC4DAT
0xFFFF0734
Table 60. IDACxDAT MMR Bit Designations
Bit
Name
Value
Description
31:28
Reserved
These bits are reserved.
27:17
Data
Data from IDACx.
16:0
Reserved
000
These bits are reserved.
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