參數(shù)資料
型號(hào)： ADUC7027BST62
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, LQFP-80
文件頁(yè)數(shù)： 47/80頁(yè)
文件大?。?/td> 840K
代理商： ADUC7027BST62
Preliminary Technical Data
ADuC702x Series
Rev. PrB | Page 47 of 80
PWMCH0
2 x PWMDAT1
2 x PWMDAT1
PWMCH0
0H
0L
PWMDAT0
PWMDAT0
4 x (GDCLK + 1 ) x t
CORE
Figure 25: typical PWM signals with high frequency gate chopping enabled
on both high-side and low-side switches
PWM shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the
PWMTRIP
pin provides an instantaneous,
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the OFF state, i.e. high state. In addition, the
PWMSYNC pulse is disabled. The
PWMTRIP
pin has an
internal pull-down resistor so that if the pin becomes
disconnected the PWM will be disabled. The state of the
PWMTRIP
pin can be read from Bit 3 of the PWMSTA
register.
On the occurrence of a PWM shutdown command, a
PWMTRIP
interrupt will be generated, internal timing of the
three-phase timing unit of the PWM controller is stopped.
Following a PWM shutdown, the PWM can only be re-enabled
(in a
PWMTRIP
interrupt service routine, for example) by
writing to all of the PWMDAT0, PWMCH0, PWMCH1 and
PWMCH2 registers. Provided the external fault has been
cleared and the
PWMTRIP
has returned to a high level,
internal timing of the three-phase timing unit resumes and new
duty-cycle values are latched on the next PWMSYNC
boundary.
PWM MMRs interface
The PWM block is controlled via the following nine MMRs:
-
PWMCON
: control register, enable the PWM, choose the
update rate
-
PWMSTA
: reflects the status of the PWM
-
PWMDAT0
: unsigned 16-bit register for switching period
-
PWMDAT1
: unsigned 10-bit register for dead time
-
PWMCFG
: gate chopping
-
PWMCH0,CH1,CH2
: channel duty cycle for the three
phases
-
PWMEN
: allows enabling channel outputs and crossover. See
bit definition Table 28.
-
PWMDAT2
: unsigned 10-bit register for PWM sync pulse
width.
Table 25: PWMCON MMR Bit Descriptions
Bit
7-5
4
Name
PWM_SYNCSEL
Description
Reserved
External sync select
Set to use external sync
Cleared to use internal sync
External sync select
Set to select external synchronous sync signal
Cleared for asynchronous sync signal
Double Update Mode
Set to ‘1’ by the user to enable double update mode
Clear to ‘0’ by the user to enable single update mode
PWM synchronisation enable
Set by user to enable synchronisation
Cleared by user to disable synchronisation
PWM Enable Bit
Set to ‘1’ by the user to enable the PWM
Clear to ‘0’ by the user to disable the PWM. Also cleared automatically with
PWMTRIP
Table 26: PWMSTA MMR Bit Descriptions
Description
Reserved
PWM sync interrupt bit
3
PWM_EXTSYNC
2
PWMDBL
1
PWM_SYNC_EN
0
PWMEN
Bit
15-10
9
Name
PWMSYNCINT
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