參數(shù)資料
型號(hào)： ADUC7027BST62
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, LQFP-80
文件頁(yè)數(shù)： 27/80頁(yè)
文件大?。?/td> 840K
代理商： ADUC7027BST62
Preliminary Technical Data
ADuC702x Series
Rev. PrB | Page 27 of 80
OUTPUT
CODE
0111 1111 1111
0111 1111 1110
0111 1111 1101
1000 0000 0010
1000 0000 0001
1000 0000 0000
-V
REF
+ 1LSB
VOLTAGE INPUT (Vin+ - Vin-)
1LSB =
2x
V
REF
4096
+V
REF
- 1LSB
0LSB
0000 0000 0001
0000 0000 0000
1111 1111 1111
Figure 9: ADC transfer function in differential mode
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC will convert the analog input and provide a
12-bit result in the ADC data register.
The top 4 bits are the sign bits and the 12-bit result is placed
from bit 16 to 27 as shown in Figure 10. Again, it should be
noted that in fully differential mode, the result is represented in
two’s complement format, and in pseudo differential and single-
ended mode, the result is represented in straight binary format.
12-bit ADC RESULT
SIGN BITS
15
16
0
27
31
-
ADCGN:
Gain calibration register. 10-bit register
Figure 10: ADC Result Format
The same format is used in DACxDAT, simplifying the software.
ADC MMRS interface
The ADC is controlled and configured via a number of MMRs
that are listed below and described in detail in the following
pages:
-
ADCCON:
ADC Control Register allows the programmer to
enable the ADC peripheral, to select the mode of operation of
the ADC, either Single-ended, pseudo-differential or fully
differential mode and the conversion type. This MMR is
described Table 7.
-
ADCCP:
ADC positive Channel selection Register
-
ADCCN:
ADC negative Channel selection Register
ADCSTA:
ADC Status Register, indicates when an ADC
conversion result is ready. The ADCSTA register contains
only one bit, bit (bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion generating an
ADC interrupt, it is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the
ADCBusy pin. This pin is high during a conversion. When
the conversion is finished, ADCBusy goes back low. This
information can be available on P0.3 (see chapter on GPIO) if
enabled in ADCCON register.
ADCDAT:
ADC Data Result Register, hold the 12-bit ADC
result as shown Figure 10
-
ADCRST:
ADC Reset Register. Resets all the ADC registers
to their default value.
-
ADCOF:
Offset calibration register. 10-bit register
Table 7: ADCCON MMR Bit Designations
Bit
7
Description
Enable Conversion
Set
by the user to enable conversion mode
Cleared
by the user to disable conversion mode
Enable ADC
BUSY
Set
by the user to enable the ADC
BUSY
pin
Cleared
by the user to disable the ADC
BUSY
pin
ADC power control:
Set
by the user to place the ADC in normal mode, the ADC must be powered up for at least 500uS before it will convert
correctly.
Cleared
by the user to place the ADC in power-down mode
Conversion Mode:
6
5
00
Single Ended Mode
01
10
11
Conversion Type:
Differential Mode
Pseudo-Differential Mode
Reserved
4-3
2-0
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